Improving display contrast

US9564563B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9564563-B2
Application numberUS-201213261922-A
CountryUS
Kind codeB2
Filing dateDec 19, 2012
Priority dateDec 20, 2011
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There is herein described electronic components with improved display contrast and a method of manufacturing such electronic components. More particularly, there is described electronic components having improved display contrast by using a non-transparent or substantially non-transparent material ( 520 ) to block light from an emitter source ( 512, 514, 516 ) to surrounding components such as emitters, sensors or components of this nature.

First claim

Opening claim text (preview).

The invention claimed is: 1. An LED array, comprising: at least two raised mesa areas; located between the at least two raised mesa areas there is a trench; on the upper surface of the at least two raised mesa areas there are pixels and N-bus formations along with an annealed metal area and a p-metal layer; wherein the trench is at least partially filled with a non-transparent or substantially non-transparent material capable of blocking light emitted from within the LED; and wherein the non-transparent or substantially non-transparent material is selected from any suitable polymeric material such as any one of or any combination of the following: polyimide; epoxy; and benzocyclobutene. 2. An LED array according to claim 1 , wherein the LED array is a micro-LED array. 3. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material is used to reduce unwanted crosstalk and thereby provide improved display contrast for LED and micro-LED arrays. 4. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material therefore fills the trench in-between adjacent pixels. 5. An LED array according to claim 1 , wherein sufficient material should be introduced so that redirected light should be absorbed and preventing from being emitted from the upper surface. 6. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material fully occupies the trench or simply forms a layer. 7. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material functions as an interlayer dielectric. 8. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material is selected from any appropriate material that is capable of blocking light. 9. An LED array according to claim 1 , wherein there is a combination of different polymers forming a light blocking layer; and wherein there is a combination of polymer and other dielectric layers comprising at least one of a silicon nitride and silicon dioxide. 10. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material forms a layer which is non-transparent or substantially non-transparent to light at the emission wavelength of the LED array. 11. An LED array according to claim 1 , wherein the non-transparent or substantially non-transparent material in polymeric form allows metals such as deposited p-metal layer to be conformably deposited thereby further reducing the light scattering from the trench; and wherein the polymeric material also provides optical and electrical isolation between emitters or between an emitter and any adjacent structure. 12. An LED array according to claim 1 , wherein the deposited non-transparent or substantially non-transparent material also functions to effectively isolate each pixel and p-contact from n-contacts, thereby eliminating the undesirable electric crosstalk and improving the device reliability. 13. An LED array, comprising: at least two raised mesa areas; located between the at least two raised mesa areas there is a trench; on the upper surface of the at least two raised mesa areas there are pixels and N-bus formations along with an annealed metal area and a p-metal layer; wherein the trench is at least partially filled with a non-transparent or substantially non-transparent material capable of blocking light emitted from within the LED; wherein there is a combination of different polymers forming a light blocking layer; and wherein there is a combination of polymer and other dielectric layers comprising at least one of a silicon nitride and silicon dioxide. 14. An LED array according to claim 13 , wherein the LED array is a micro-LED array. 15. An LED array according to claim 13 , wherein the non-transparent or substantially non-transparent material functions as an interlayer dielectric. 16. An LED array, comprising: at least two raised mesa areas; located between the at least two raised mesa areas there is a trench; on the upper surface of the at least two raised mesa areas there are pixels and N-bus formations along with an annealed metal area and a p-metal layer; wherein the trench is at least partially filled with a non-transparent or substantially non-transparent material capable of blocking light emitted from within the LED; and wherein the non-transparent or substantially non-transparent material forms a layer which is non-transparent or substantially non-transparent to light at the emission wavelength of the LED array. 17. An LED array according to claim 16 , wherein the LED array is a micro-LED array. 18. An LED array according to claim 16 , wherein the non-transparent or substantially non-transparent material functions as an interlayer dielectric. 19. An LED array, comprising: at least two raised mesa areas; located between the at least two raised mesa areas there is a trench; on the upper surface of the at least two raised mesa areas there are pixels and N-bus formations along with an annealed metal area and a p-metal layer; wherein the trench is at least partially filled with a non-transparent or substantially non-transparent material capable of blocking light emitted from within the LED; wherein the non-transparent or substantially non-transparent material in polymeric form allows metals such as deposited p-metal layer to be conformably deposited thereby further reducing the light scattering from the trench; and wherein the polymeric material also provides optical and electrical isolation between emitters or between an emitter and any adjacent structure. 20. An LED array according to claim 19 , wherein the LED array is a micro-LED array. 21. An LED array according to claim 19 , wherein the non-transparent or substantially non-transparent material functions as an interlayer dielectric. 22. An LED array, comprising: at least two raised mesa areas; located between the at least two raised mesa areas there is a trench; on the upper surface of the at least two raised mesa areas there are pixels and N-bus formations along with an annealed metal area and a p-metal layer; wherein the trench is at least partially filled with a non-transparent or substantially non-transparent material capable of blocking light emitted from within the LED; and wherein the deposited non-transparent or substantially non-transparent material also functions to effectively isolate each pixel and p-contact from n-contacts, thereby eliminating the undesirable electric crosstalk and improving the device reliability. 23. An LED array according to claim 22 , wherein the LED array is a micro-LED array. 24. An LED array according to claim 22 , wherein the non-transparent or substantially non-transparent material functions as an interlayer dielectric.

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What does patent US9564563B2 cover?
There is herein described electronic components with improved display contrast and a method of manufacturing such electronic components. More particularly, there is described electronic components having improved display contrast by using a non-transparent or substantially non-transparent material ( 520 ) to block light from an emitter source ( 512, 514, 516 ) to surrounding components such as …
Who is the assignee on this patent?
Oculus Vr Llc
What technology area does this patent fall under?
Primary CPC classification H01L33/58. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).