Direct wafer bonding

US9564548B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9564548-B2
Application numberUS-201414461929-A
CountryUS
Kind codeB2
Filing dateAug 18, 2014
Priority dateDec 3, 2010
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.

First claim

Opening claim text (preview).

What is claimed is: 1. An assembly comprising: a first subassembly comprising a first wafer substrate and a first bonding layer upon the first wafer substrate, the first bonding layer being lattice matched to the first wafer substrate; and a second subassembly comprising a second wafer substrate and a second bonding layer upon the second wafer substrate, the second bonding layer being lattice matched to the second wafer substrate, wherein the first and second bonding layers are directly bonded to form an interface and to form the assembly; and wherein the first bonding layer is an (Al)(Ga)InP(As)(Sb) layer and the second bonding layer is an (Al)(Ga)InP(As)(Sb) layer. 2. The assembly of claim 1 , wherein the assembly has a bond strength of greater than or equal to about 4 J/m 2 across the bond interface between the first and second bonding layers. 3. The assembly of claim 1 , wherein the assembly has an optical transmittance greater than or equal to about 97% across the bond interface between the first and second bonding layers. 4. The assembly of claim 1 , wherein the first and second bonding layers have a dopant concentration equal to or greater than about 5×10 18 /cm 3 . 5. The assembly of claim 1 , wherein the first and second bonding layers have a dopant concentration lower than about 5×10 18 /cm 3 . 6. The assembly of claim 1 , wherein the first and second bonding layers are similarly doped. 7. The assembly of claim 1 , wherein the first and second bonding layers are dissimilarly doped. 8. The assembly of claim 1 , wherein the bonding layers form a tunnel junction. 9. The assembly of claim 1 , wherein the first and second wafer substrates comprise one or more layers selected from the group consisting of Si, Ge, GaAs-based, InP-based, GaP-based, GaSb-based, and Ga(In)N-based materials. 10. The assembly of claim 1 , wherein the first and second wafer substrates comprise Si or Ge or a combination thereof. 11. The assembly of claim 1 , wherein either or both of the first and second wafer substrates comprises one or more semiconductor layers. 12. The assembly of claim 1 , wherein either or both of the first and second wafer substrates comprises one or more semiconductor devices. 13. The assembly of claim 12 , wherein the one or more semiconductor devices is an InP-based device. 14. The assembly of claim 13 , wherein the InP-based device is a solar cell. 15. A solar cell comprising the assembly of claim 1 . 16. A method for making a bonded assembly, comprising: providing a first wafer; forming a first bonding layer upon the first wafer to form a first subassembly; providing a second wafer; forming a second bonding layer upon the second wafer to form a second subassembly; and directly bonding the first bonding layer to the second bonding layer to form an interface and to form the bonded assembly; wherein the first and second bonding layers are lattice matched to the first and second wafers, respectively; the first bonding layer is an (Al)(Ga)InP(As)(Sb) layer; and the second bonding layer is an (Al)(Ga)InP(As)(Sb) layer. 17. The method of claim 16 , wherein the first and second bonding layers are bonded at a temperature between about 300° C. and about 500° C. 18. The method of claim 16 , wherein the first and second bonding layers are bonded at a pressure of between about 20 psi and about 50 psi. 19. The method of claim 16 , wherein the bonded assembly has a bond strength of greater than or equal to about 4 J/m 2 across the interface between the first and second bonding layers. 20. The method of claim 16 , wherein the first and second wafers comprise one or more layers formed from a material selected from the group consisting of Si, Ge, GaAs-based, InP-based, GaP-based, GaSb-based, and Ga(In)N-based materials.

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What does patent US9564548B2 cover?
The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer…
Who is the assignee on this patent?
Boeing Co
What technology area does this patent fall under?
Primary CPC classification H10P10/128. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).