Non-volatile memory devices and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-9564519-B2
Application number	US-201414457220-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Nov 13, 2013
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

First claim

What is claimed is:

1. A method of manufacturing a non-volatile memory device, comprising:
alternately stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate, wherein the plurality of conductive layers comprise a silicon material;
forming an opening that exposes a portion of the substrate and lateral surfaces of the insulating layers and the conductive layers;
forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers;
forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer;
forming a channel region on the tunneling layer;
forming a separation opening through the plurality of insulating layers and the plurality of conductive layers;
forming a metal layer in the separation opening;
performing a heat treatment process on the metal layer and the plurality of conductive layers to generate a metal silicide; and
forming a separation layer in the separation opening,
wherein the anti-oxidation layer remains between the plurality of conductive layers and the gate dielectric after forming the separation layer in the separation opening.

2. The method of claim 1 , wherein the anti-oxidation layer comprises a dielectric material that is different than a dielectric material of a portion of the blocking layer that directly contacts the anti-oxidation layer.

3. The method of claim 1 , wherein the anti-oxidation layer is a discontinuous layer that covers the exposed lateral surfaces of the conductive layers but that does not cover the exposed lateral surfaces of insulating layers that are disposed between two conductive layers.

4. The method of claim 1 , wherein portions of the anti-oxidation layer that are formed on the exposed lateral surfaces of the conductive layers have a substantially uniform thickness.

5. The method of claim 1 , wherein the blocking layer is a multi-layer structure having a first blocking layer that includes a low dielectric constant material that contacts the electric charge storage layer and a second blocking layer that includes a high dielectric constant material between the first blocking layer and the anti-oxidation layer.

6. The method of claim 5 , wherein the anti-oxidation layer has a dielectric constant that is lower than a dielectric constant of the first blocking layer.

7. The method of claim 5 , wherein a thickness of the anti-oxidation layer is smaller than a thickness of the first blocking layer.

8. The method of claim 1 , wherein a maximum difference between a first thickness of a portion of the anti-oxidation layer that is formed on the exposed lateral surface of one of the conductive layers and a second thickness of a portion of the anti-oxidation layer that is formed on the exposed lateral surface of another one of the conductive layers is less than or equal to 25% of an average thickness of the anti-oxidation layer.

9. The method of claim 1 , wherein the conductive layers comprise gate electrodes.

10. The method of claim 9 , wherein the anti-oxidation layer extends along the channel region perpendicular to the top surface of the substrate from a bottom gate electrode that is closest to the substrate to a top gate electrode that is farthest away from the substrate.

11. The method of claim 9 , wherein lateral surfaces of the anti-oxidation layer that are opposite the gate electrodes are not coplanar with lateral surfaces of the interlayer insulating layers.

12. The method of claim 1 , wherein the blocking layer is formed using an oxygen-containing gas.

13. The method of claim 1 , wherein the anti-oxidation layer is formed via an atomic layer deposition process or via a chemical vapor deposition process at a temperature that does not substantially oxidize exposed portions of the conductive layers.

14. A method of manufacturing a non-volatile memory device, comprising
alternately stacking insulating layers and conductive layers on a substrate;
forming an opening that exposes a portion of the substrate and lateral surfaces of the insulating layers and the conductive layers;
forming an epitaxial layer on the exposed portion of the substrate in the opening;
forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers;
forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and
forming a channel region on the tunneling layer and the epitaxial layer.

15. The method of claim 14 , further comprising:
forming a separation opening through the insulating layers and the conductive layers;
forming a metal layer in the separation opening;
performing a heat treatment process on the metal layer and a silicon material of the conductive layers to generate a metal silicide; and
forming a separation layer in the separation opening,
wherein the anti-oxidation layer remains between the conductive layers and the gate dielectric after forming the separation layer in the separation opening.

16. A method of manufacturing a non-volatile memory device, the method comprising:
alternately stacking interlayer insulating layers and conductive layers on a substrate;
forming openings through the interlayer insulating layers and the conductive layers that expose the substrate;
forming an anti-oxidation layer on the conductive layers exposed through side walls of the openings;
sequentially forming a blocking layer including a high-k layer and a low-k layer, an electric charge storage layer, and a tunneling layer on the anti-oxidation layer to form a gate dielectric layer;
forming a channel region on the gate dielectric layer;
forming a separation opening through the interlayer insulating layers and the conductive layers; and
forming a separation layer in the separation opening,

wherein the anti-oxidation layer remains between the conductive layers and the gate dielectric after forming the separation layer in the separation opening.

17. The method of claim 16 , wherein portions of the anti-oxidation layer that are formed on the exposed lateral surfaces of the conductive layers have a substantially uniform thickness.

18. The method of claim 16 , wherein the anti-oxidation layer comprises a dielectric material that is different than a dielectric material of a portion of the blocking layer that directly contacts the anti-oxidation layer.

19. The method of claim 16 , wherein the conductive layers comprise a silicon material.

20. The method of claim 19 , further comprising forming a metal layer in the separation opening; performing a heat treatment process on the metal layer and the conductive layers to generate a metal silicide after forming the separation opening.

Assignees

• Park Jin Taek
• Park Young Woo
• Lee Jae Duk
• Samsung Electronics Co Ltd

Inventors

• Park Jin Taek
• Park Young Woo
• Lee Jae Duk

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/7789

  Electricity · mapped topic

• H01L29/66833 Primary

  Electricity · mapped topic