Changing effective work function using ion implantation during dual work function metal gate integration

US9564505B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9564505-B2
Application numberUS-201414254939-A
CountryUS
Kind codeB2
Filing dateApr 17, 2014
Priority dateAug 12, 2008
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

First claim

Opening claim text (preview).

What is claimed is: 1. A structure comprising: a first-type field effect transistor (FET) including a gate having a high dielectric constant (high-k) layer and a single metal layer over a first type FET region and the high-k layer, the single metal layer having a first effective work function; and a second-type FET including the high-k layer and the single metal layer over a second type FET region and the high-k layer, the high-k layer further including an implanted aluminum (Al) species, the single metal layer further including the implanted aluminum (Al) species that changes the first effective work function to a different second effective work function resulting in a greater than 50 millivolt threshold voltage shift for the second type FET region when compared to the first type FET region, wherein the single metal layer is selected from the group consisting of: tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbide oxynitride (TaCNO), ruthenium oxide (RuO 2 ), and mixtures and multi-layers thereof. 2. The structure of claim 1 , further comprising a polysilicon layer over the metal layer in each of the first-type and second-type FETs. 3. The structure of claim 1 , wherein the threshold voltage shift is approximately 600 milli-Volts. 4. The structure of claim 1 , wherein the first-type FET includes an n-type FET (NFET), and the second-type FET includes a p-type FET (PFET), and a threshold voltage shift between the NFET and the PFET approaches a band edge threshold voltage shift of the PFET. 5. A structure comprising: a first-type field effect transistor (FET) including a gate having a high dielectric constant (high-k) layer and a single metal layer over a first type FET region and the high-k layer, the single metal layer having a first effective work function; and a second-type FET including the high-k layer and the single metal layer over a second type FET region and the high-k layer, the single metal layer and the high-k layer each further including an implanted aluminum (Al) species that changes the first effective work function to a different second effective work function wherein a threshold voltage shift for the second-type FET is greater than 50 milli-Volt compared to the first-type FET, wherein the single metal layer is selected from the group consisting of: tungsten (W), tantalum (Ta), aluminum (Al), ruthenium (Ru), platinum (Pt), titanium nitride (TIN), tantalum nitride (TAN), titanium carbide (TIC), tantalum carbide (TaC), tantalum carbide oxynitride (TaCNO), ruthenium oxide (RuO2), and mixtures and multi-layers thereof, the structure further comprising a polysilicon layer over the metal layer in each of the first-type and second type FETs, and wherein the threshold voltage shift is approximately 600 milli-Volts. 6. The structure of claim 5 , wherein the first-type FET includes an n-type FET (NFET), and the second-type FET includes a p-type FET (PFET), and a threshold voltage shift between the NFET and the PFET approaches a band edge threshold voltage shift of the PFET.

Assignees

Inventors

Classifications

  • the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

  • the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

  • Complementary IGFETs, e.g. CMOS · CPC title

  • the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9564505B2 cover?
Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region a…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10D64/01316. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).