Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9564465-B2
Application number	US-201414912659-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Aug 28, 2013
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated.
A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

First claim

What is claimed is:

1. A solid-state imaging apparatus, comprising:
a charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges;
a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section; and
a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section, wherein
a bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

2. The solid-state imaging apparatus according to claim 1 , wherein
the transfer transistor is formed such that a gate terminal penetrates the first semiconductor substrate and reaches the second semiconductor substrate.

3. The solid-state imaging apparatus according to claim 2 , wherein
the bonding interface is formed at a position of the gate terminal of the transfer transistor, which is closer to a drain terminal than to a source terminal.

4. The solid-state imaging apparatus according to claim 1 , wherein
in the second semiconductor substrate, formed are pixel transistors including
an amplifying transistor that amplifies a signal voltage corresponding to charges retained by at least the charge-retaining section,
a reset transistor that resets charges retained by the charge-retaining section, and
a selection transistor that selects a signal to be output to a signal line, the signal corresponding to charges read out from the charge-retaining section.

5. The solid-state imaging apparatus according to claim 4 , wherein
the gate terminal of the amplifying transistor and the charge-retaining section are connected by silicon.

6. The solid-state imaging apparatus according to claim 4 , wherein
a P-type semiconductor region is formed as a body contact that connects the amplifying transistor, the reset transistor, and the selection transistor.

7. The solid-state imaging apparatus according to claim 4 , wherein
a part of an N-type semiconductor region forming the charge-retaining section is directly connected to the amplifying transistor.

8. The solid-state imaging apparatus according to claim 4 , being configured by bonding the second semiconductor substrate that is a single-crystal silicon substrate and the first semiconductor substrate that is a silicon substrate to each other.

9. The solid-state imaging apparatus according to claim 8 , wherein
a silicon layer is formed in the bonding interface between the first semiconductor substrate and the second semiconductor substrate.

10. The solid-state imaging apparatus according to claim 9 , wherein
the silicon layer is formed by epitaxial growth.

11. The solid-state imaging apparatus according to claim 10 , wherein
silicon ions are implanted onto the silicon layer and the silicon layer is bonded to the second semiconductor substrate.

12. The solid-state imaging apparatus according to claim 1 , wherein
a light-shielding film is embedded in the first semiconductor substrate.

13. The solid-state imaging apparatus according to claim 12 , wherein
near the gate terminal of the transfer transistor, a region in which the light-shielding film is not provided is present, and
near the gate terminal of the transfer transistor, the light-shielding film is configured to be long in a direction parallel to an extending direction of the gate terminal of the transfer transistor.

14. The solid-state imaging apparatus according to claim 12 , wherein
the light-shielding film is formed of tungsten, titanium, tantalum, nickel, molybdenum, chromium, iridium, or a tungsten silicon compound.

15. The solid-state imaging apparatus according to claim 1 , wherein
the single charge-retaining section is provided corresponding to a plurality of charge accumulation sections.

16. The solid-state imaging apparatus according to claim 1 , wherein
a plurality of charge accumulation sections are multilayered in a direction in which the first semiconductor substrate and the second semiconductor substrate are laminated.

17. The solid-state imaging apparatus according to claim 1 , being configured as a planar structure.

18. The solid-state imaging apparatus according to claim 1 , being configured as a mesa structure.

19. A manufacturing method for a solid-state imaging apparatus, comprising:
a step of bonding a first semiconductor substrate formed in a charge accumulation section that accumulates photoelectrically converted charges and a second semiconductor substrate on which a charge-retaining section that retains charges accumulated in the charge accumulation section to each other; and
a step of forming a transfer transistor that transfers charges accumulated in the charge accumulation section to the charge-retaining section in the first semiconductor substrate and the second semiconductor substrate.

20. An electronic apparatus, comprising:
a solid-state imaging apparatus including
a charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges;
a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section; and
a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section, wherein

a bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

Assignees

• Sony Corp
• Sony Semiconductor Solutions Corp

Inventors

• Tayanaka Hiroshi

Classifications

• H04N25/623

  by evacuation via the output or reset lines · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/69

  SSIS comprising testing or correcting structures for circuits other than pixel cells · CPC title

• H04N25/68

  applied to defects · CPC title