Multi-stacked structures of semiconductor packages

Patent metadata

Field	Value
Publication number	US-9564417-B2
Application number	US-201514848415-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Sep 24, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A multi-stacked structure of semiconductor packages includes a plurality of substrates stacked in a vertical direction, semiconductor packages mounted on each substrate of the plurality of the substrates, a heat release column extending commonly through the plurality of the substrates and overlapping at least one semiconductor package serving as a heat generation source among the semiconductor packages in the vertical direction, and a heat dissipation part thermally connected to one end of the heat release column.

First claim

What is claimed is:

1. A multi-stacked structure of semiconductor packages, comprising:
a plurality of substrates stacked in a vertical direction, wherein at least one substrate comprises signal wirings and ground wirings;
semiconductor packages mounted on each substrate of the plurality of substrates;
a heat release column extending substantially vertically through the plurality of substrates, the heat release column overlapping at least one of the semiconductor packages serving as a heat generation source, wherein the heat release column is in contact with the ground wirings in the at least one substrate, and is spaced apart from the signal wirings in the at least one substrate; and
a heat dissipation part thermally connected to one end of the heat release column.

2. The multi-stacked structure of claim 1 , wherein the heat release column is directly on a maximum heat generation package.

3. The multi-stacked structure of claim 2 , wherein the maximum heat generation package is mounted on a lower surface of a lowermost substrate among the plurality of substrates.

4. The multi-stacked structure of claim 1 , wherein the heat release column is connected to a top surface of one of the ground wirings included in a lowermost substrate among the plurality of substrates.

5. The multi-stacked structure of claim 4 , further comprising a thermal conductive adhesive interposed between a bottom of the heat release column and the top surface of the one of the ground wirings.

6. The multi-stacked structure of claim 5 , wherein the thermal conductive adhesive comprises a thermal interface material (TIM).

7. The multi-stacked structure of claim 1 , further comprising an insulation layer pattern surrounding a sidewall of the heat release column.

8. The multi-stacked structure of claim 1 , further comprising a case that accommodates the plurality of substrates,
wherein the heat dissipation part comprises:
a first thermal conductive adhesive in contact with the heat release column;
a second thermal conductive adhesive in contact with the case; and
a thermal dissipation plate between the first thermal conductive adhesive and the second thermal conductive adhesive.

9. The multi-stacked structure of claim 1 , wherein the heat release column comprises a plurality of stacked heat release columns which partially overlap each other along the vertical direction.

10. The multi-stacked structure of claim 9 , wherein each substrate comprises signal wirings and ground wirings, and
wherein neighboring stacked heat release columns among the plurality of stacked heat release columns are connected to each other by the ground wirings.

11. A multi-stacked structure of semiconductor packages, comprising:
a first substrate, a second substrate and a third substrate sequentially stacked in a vertical direction;
a plurality of semiconductor packages mounted on the first substrate, the second substrate and the third substrate;
a first heat release column extending through the first substrate and in contact with a semiconductor package mounted on the second substrate; and
a second heat release column overlapping the first heat release column in the vertical direction, the second heat release column extending through the third substrate and the second substrate.

12. The multi-stacked structure of claim 11 , wherein the semiconductor package in contact with the first heat release column is a maximum heat generation package.

13. The multi-stacked structure of claim 11 , wherein the semiconductor package in contact with the first heat release column comprises a mounting surface and a non-mounting surface, the mounting surface being connected to the second substrate via conductive members, the non-mounting surface facing the mounting surface, and
further comprising a thermal conductive adhesive between a top surface of the first heat release column and the non-mounting surface.

14. The multi-stacked structure of claim 11 , wherein each of the first substrate, the second substrate and the third substrate comprises ground wirings and signal wirings, and
wherein the second heat release column extends partially through the second substrate such that the second heat release column is connected to a top surface of one of the ground wirings in the second substrate.

15. A multi-stacked structure of semiconductor packages, comprising:
a first substrate, a second substrate and a third substrate sequentially stacked in a vertical direction;
a plurality of semiconductor packages mounted on the first substrate, the second substrate and the third substrate;
a first heat release column extending through an upper portion of the first substrate and a lower portion of the second substrate;
a second heat release column extending through an upper portion of the second substrate and a lower portion of the third substrate; and
a third heat release column extending through an upper portion of the third substrate and thermally connected to a heat dissipation part.

16. The multi-stacked structure of claim 15 , wherein lateral surfaces of the first heat release column and second heat release column partially overlap in a horizontal direction of the multi-stacked structure, and wherein lateral surfaces of the second and third heat release columns partially overlap in the horizontal direction.

17. The multi-stacked structure of claim 15 , wherein the second substrate comprises ground wirings, wherein the first heat release column is in contact with at least one of the ground wirings in the second substrate, and wherein the second heat release column is in contact with at least one of the ground wirings in the second substrate.

18. The multi-stacked structure of claim 17 , wherein the first and second heat release columns form a parallel connection via the ground wirings.

19. The multi-stacked structure of claim 15 , further comprising an insulation layer pattern surrounding a sidewall of the first and second heat release columns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Jae-Bum
• Kwon Cheol
• Yun Jong-Yun
• Kong Do-Il
• Hur Sung-Chul

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W40/778

  in encapsulations · CPC title