Methods and apparatus for reducing spatial overlap between routing wires

Patent metadata

Field	Value
Publication number	US-9564394-B1
Application number	US-201414546320-A
Country	US
Kind code	B1
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.

First claim

What is claimed is:

1. Interconnect circuitry, comprising:
a routing tile in a sequence of tiles, wherein the routing tile comprises:
a first wire in a first metal layer that has a first endpoint in a first track;
a second wire in the first metal layer that has a second endpoint in a second track that is different than the first track;
a third wire in the first metal layer that has a third endpoint in a third track that is different than the first and second tracks;
a fourth wire in the first metal layer that runs along the first track; and
a connection from the third wire to the fourth wire through at least two via connections and a track in a second metal layer.

2. The interconnect circuitry of claim 1 , wherein each routing tile in the sequence of tiles has the same layout.

3. The interconnect circuitry of claim 1 , wherein the routing tile further comprises:
a fifth wire in the first metal layer that is routed from the second track to the third track and from the third track to a fourth track.

4. The interconnect circuitry of claim 3 , wherein the routing tile further comprises:
a sixth wire in the first metal layer that is routed from the fourth track to a fifth track.

5. The interconnect circuitry of claim 4 , wherein the routing tile further comprises:
a seventh wire in the first metal layer that has a fourth endpoint in the fifth track; and
an eighth wire in the first metal layer that has a fifth endpoint in the second track.

6. The interconnect circuitry of claim 5 , wherein the routing tile further comprises:
an additional connection from the seventh wire to the eighth wire through at least two additional via connections and an additional track in the second metal layer.

7. The interconnect circuitry of claim 1 , wherein the routing tile further comprises:
a fifth wire in the first metal layer that is routed from a fourth track to the third track.

8. The interconnect circuitry of claim 7 , wherein the routing tile further comprises:
a sixth wire in the first metal layer that is routed from the first track to the second track and from the second track to the fourth track.

9. A method for arranging wires in interconnection circuitry on an integrated circuit, comprising:
forming a first wire that starts in a first routing tile and extends into a second routing tile;
forming a second wire that starts in the first routing tile and that ends in the second routing tile, wherein the first and second wires overlap each other on two adjacent tracks from at least a portion of the first routing tile to at least a portion of the second routing tile, and wherein the first and second wires have different starting points; and
coupling the second wire to the first wire in the first routing tile, wherein coupling the second wire to the first wire comprises:
forming a first driver that receives a signal from the second wire in the first routing tile; and
forming a second driver that drives the signal onto the first wire in the first routing tile.

10. The method of claim 9 , wherein the first and second routing tiles are adjacent.

11. The method of claim 9 , further comprising:
configuring routing circuitry that routes the signal from the first driver to the second driver.

12. The method of claim 9 , further comprising:
forming a crossover connection in the first routing tile, wherein the crossover connection couples the second wire from a first track of the two adjacent tracks to a second track, and wherein the second track is separated by at least one additional track from each of the two adjacent tracks.

13. The method of claim 12 , wherein forming the crossover connection further comprises:
forming a first via connection between the first track in a first metal layer and an additional track in a second metal layer;
forming a second via connection between the second track in the first metal layer and the additional track in the second metal layer; and
forming a wire connection in the additional track in the second metal layer between the first and second via connections.

14. A method for forming a routing tile with T tracks, comprising:
forming T terminals numbered from 1 to T on a first edge of the routing tile;
forming T terminals numbered from 1 to T on a second edge of the routing tile that opposes the first edge; and
forming a plurality of conductive traces between the T terminals on the first edge of the routing tile and the T terminals on the second edge of the routing tile, wherein at least one conductive trace of the plurality of conductive traces includes at least two via connections that link together nonadjacent terminals on the first and second edges of the routing tile.

15. The method of claim 14 , wherein the routing tile has at most (T-1) via connections.

16. The method of claim 14 , wherein forming the plurality of conductive traces further comprises:
determining whether T is an odd number.

17. The method of claim 16 , further comprising:
in response to determining that T is an odd number, forming a conductive trace in the plurality of conductive traces between terminal number T on the first edge and terminal number T-1 on the second edge.

18. The method of claim 16 , further comprising:
in response to determining that T is not an odd number, forming a conductive trace in the plurality of conductive traces between terminal number T-1 on the first edge and terminal number T on the second edge.

19. The method of claim 14 , wherein forming the plurality of conductive traces further comprises:
forming an additional conductive trace in the plurality of conductive traces for each terminal with an even number i greater than three on the first edge and a terminal with number i-2 on the second edge.

20. The method of claim 14 , wherein forming the plurality of conductive traces further comprises:
forming an additional conductive trace for each terminal with an odd number i smaller than T on the first edge and a terminal with number i+2 on the second edge.

21. The method of claim 14 , further comprising:
generating at least two instances of the routing tile; and
coupling the at least two instances of the routing tile to form the interconnection circuitry.

22. The method of claim 21 , wherein any pair of conductive traces of the plurality of conductive traces is adjacent for at most one instance of the routing tile.

Assignees

• Altera Corp

Inventors

• Roth Aron Joseph
• Chromczak Jeffrey Christopher
• Chan Michael

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/01 Primary

  Manufacture or treatment · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• H01L21/768

  Electricity · mapped topic

• G06F17/5077

  Physics · mapped topic