Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9564368-B2
Application number	US-201615077351-A
Country	US
Kind code	B2
Filing date	Mar 22, 2016
Priority date	Aug 25, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate with a first region, a second region, and a third region between the first and second regions;
first active patterns protruding upward from the first region of the substrate, extending in a first direction crossing the first to third regions, and being spaced apart from each other in a second direction crossing the first direction;
second active patterns protruding upward from the second region of the substrate, extending in the first direction, and being spaced apart from each other in the second direction, first distances between adjacent ones of the first active patterns are different from second distances between adjacent ones of the second active patterns when measured in the second direction;
a first gate structure crossing the first active patterns; and
a second gate structure crossing the second active patterns,
wherein the third region is defined by a trench, which is provided on the substrate and between the first and second regions,
sidewall surfaces of the first active patterns are aligned along the second direction at a boundary between the first and third regions, and
sidewall surfaces of the second active patterns are aligned along the second direction at a boundary between the second and third regions.

2. The device of claim 1 , wherein when measured in the first direction, a largest width of the trench is substantially equal to a distance between the sidewall surfaces of the first and second active patterns.

3. The device of claim 1 , wherein when viewed in a sectional view, a top surface of the first region of the substrate meets a sidewall of the trench at the boundary of the first and third region and a top surface of the second region of the substrate meets an opposite sidewall of the trench at the boundary of the second and third regions.

4. The device of claim 1 , wherein the first gate structure serves as a part of a memory cell transistor, and
the second gate structure serves as a part of a peripheral circuit transistor.

5. The device of claim 4 , wherein the second distances are larger than the first distances.

6. A semiconductor device, comprising:
a substrate with a cell array region, a peripheral circuit region, and a buffer region, the cell array region and the peripheral circuit region being spaced apart from each other in a first direction with the buffer region interposed there between;
first active patterns protruding upward from the cell array region of the substrate, extending in the first direction, and being spaced apart from each other in a second direction crossing the first direction;
second active patterns protruding upward from the peripheral circuit region of the substrate, extending in the first direction, and being spaced apart from each other in the second direction, distances between adjacent ones of the first active patterns are smaller than those between adjacent ones of the second active patterns when measured in the second direction;
a first gate structure crossing the first active patterns and serving as a part of a memory cell transistor; and
a second gate structure crossing the second active patterns and serving as a part of a peripheral circuit transistor,
wherein the buffer region is defined by a single trench, which is provided on the substrate and between the cell array region and the peripheral circuit region.

7. The device of claim 6 , wherein sidewall surfaces of the first active patterns are aligned along the second direction at a boundary between the cell array region and the buffer region, and
sidewall surfaces of the second active patterns are aligned along the second direction at a boundary between the peripheral circuit region and the buffer region.

8. The device of claim 7 , wherein when measured in the first direction, a largest width of the single trench is substantially equal to a distance between the sidewall surfaces of the first and second active patterns.

9. The device of claim 7 , wherein when viewed in a sectional view, a top surface of the cell array region of the substrate meets a sidewall of the single trench at the boundary of the cell array region and the buffer region and a top surface of the peripheral circuit region of the substrate meets an opposite sidewall of the single trench at the boundary of the peripheral circuit region and the buffer region.

10. A semiconductor device comprising:
a substrate including a first region and a second region, the first and second regions being spaced apart from each other in a first direction with a single trench provided on the substrate and between the first and second regions;
a first transistor provided on the first region, wherein the first transistor comprises: first active patterns protruding upward from the first region of the substrate, extending in the first direction, and being spaced apart from each other in a second direction crossing the first direction; a first gate structure crossing the first active patterns; and first source/drain regions disposed at both sides of the first gate structure; and
a second transistor provided on the second region, wherein the second transistor comprises: second active patterns protruding upward from the second region of the substrate, extending in the first direction, and being spaced apart from each other in the second direction; a second gate structure crossing the second active patterns; and second source/drain regions disposed at both sides of the second gate structure,
wherein first distances between adjacent ones of the first active patterns are different from second distances between adjacent ones of the second active patterns when measured in the second direction.

11. The device of claim 10 , wherein the second distances are larger than the first distances.

12. The device of claim 10 , wherein, when viewed in a plan view, first ends of the first active patterns adjacent to the single trench are aligned along the second direction, and
second ends of the second active patterns adjacent to the single trench are aligned along the second direction.

13. The device of claim 12 , wherein when measured in the first direction, a largest width of the trench is substantially equal to a distance between the first ends of the first active patterns and the second ends of the second active patterns.

14. The device of claim 10 , wherein the first gate structure serves as a part of a memory cell transistor, and
the second gate structure serves as a part of a peripheral circuit transistor.

Assignees

• Baek Sanghoon
• Park Jae-Ho
• Yang Seolun
• Song Taejoong
• Oh Sang-Kyu
• Samsung Electronics Co Ltd

Inventors

• Baek Sanghoon
• Park Jae-Ho
• Yang Seolun
• Song Taejoong
• Oh Sang-Kyu

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title