Apparatus and method for rounded ONO formation in a flash memory device

Patent metadata

Field	Value
Publication number	US-9564331-B2
Application number	US-201213540373-A
Country	US
Kind code	B2
Filing date	Jul 2, 2012
Priority date	Jul 2, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

First claim

What is claimed is:

1. A memory device, comprising:
a semiconductor layer, including a source/drain region;
an isolation region;
a first insulator disposed above said source/drain region;
a charge trapping layer comprising nitride disposed above said first insulator, wherein said charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein tops of said first and second tips are above a top surface of said bulk portion and form obtuse angles between said top surface of said bulk portion and said tops of said first and second tips;
a second insulator disposed above said charge trapping layer; and
a polysilicon gate structure disposed above said second insulator,
wherein said source/drain region comprises a top surface that is rounded across a width of the source/drain region.

2. The memory device of claim 1 , wherein said polysilicon gate structure includes an obtuse bottom profile including first and second corners corresponding to said first and second tips, wherein said corners are rounded.

3. The memory device of claim 1 , wherein said angle ranges between 120 to 125 degrees.

4. The memory device of claim 1 , wherein said first and second tips extend beyond said source/drain region.

5. The memory device of claim 1 , wherein said top surface is continuously rounded to provide a uniformly rounded shape across the width of said source/drain region.

6. The memory device of claim 5 , wherein said first insulator, said charge trapping layer, said second insulator and said polysilicon gate structure are rounded in conformance with the top surface of the source/drain region to increase a width of a channel in the memory device.

7. The memory device of claim 6 , wherein a width of said polysilicon gate structure is wider than the width of the source/drain region.

Assignees

• Fang Shenqing
• Chen Tung-Sheng
• Thurgate Tim
• Li Di
• Cypress Semiconductor Corp

Inventors

• Fang Shenqing
• Chen Tung-Sheng
• Thurgate Tim
• Li Di

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L27/11568

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L21/28282 Primary

  Electricity · mapped topic