Methods of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-9564325-B2
Application number	US-201414328283-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Oct 14, 2013
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
preparing a lower structure including a first stack structure including sequentially stacked first etch target layers and a second stack structure disposed on the first stack structure and including second etch target layers each having a width less than those of the first etch target layers;
forming a first hard mask layer to cover the first and second stack structures of the lower structure, the first hard mask layer having a level top surface;
forming a second hard mask pattern on the first hard mask layer, the second hard mask pattern having a width greater than that of the second stack structure but less than that of the first stack structure;
patterning the first hard mask layer using the second hard mask pattern as an etch mask to form a first hard mask pattern and to expose at least a portion of a top surface of the first stack structure;
removing the second hard mask pattern and simultaneously removing an exposed portion of an uppermost first etch target layer of the exposed first stack structure;
reducing a size of the first hard mask pattern, wherein the first hard mask pattern covers the second stack structure after the reducing process; and
etching the first stack structure using the first hard mask pattern as an etch mask.

2. The method of claim 1 , wherein reducing a size of the first hard mask pattern and etching the first stack structure using the first hard mask pattern as an etch mask are repeated until a lowermost first etch target layer of the first stack structure is etched.

3. The method of claim 1 , wherein the first etch target layers include a first sacrificial layer and a first inter-gate dielectric which are sequentially stacked, and
wherein the second hard mask pattern includes materials included in the first sacrificial layer and the first inter-gate dielectric.

4. The method of claim 1 , wherein forming the first hard mask layer comprises:
coating a composition for the first hard mask layer on the lower structure; and
curing the composition.

5. The method of claim 4 , wherein an ultrasonic wave is applied to the composition at least once during the process of coating the composition for the first hard mask layer on the lower structure and/or curing the composition.

6. The method of claim 4 , wherein the composition includes a first polymer and a second polymer, wherein a weight-average molecular weight of the first polymer is at least 1.5 times that of the second polymer.

7. The method of claim 4 , wherein the composition includes at least one of the compounds of Formula (1) or Formula (2) below:

wherein in Formula (1), p is an integer ranging from 100 to 3000, R 1 is a methylene or an arylene; R 2 and R 3 are each independently a hydroxyl group, halogen or C 1 -C 19 alkyl group; and R 4 is C 1 -C 19 alkyl group or aromatic cyclic compound, and
wherein in Formula (2), n+m is an integer ranging from 100 to 3000; R 5 is a methylene or an aryiene; and R 6 is C 1 -C 19 alkyl group or aromatic cyclic compound.

8. The method of claim 7 , wherein the composition further includes a surfactant.

9. The method of claim 8 , wherein the surfactant is a cationic, anionic or non-ionic surfactant.

10. The method of claim 8 , wherein the surfactant is at least one of DBS (dodecythenzene sulfonic acid)[C 12 H 25 C 6 H 4 SO 3 H], polyoxyethylene(23) lauryl ether)[C 12 H 25 (OCH 2 CH 2 ) 23 OH], polyethylene glycol sorbitan monolaurate, polyoxyethylene isooctylphenyl ether [CH 3 (CH 2 ) x (OCH 2 CH 2 ) y OCH 2 COOH, where x is 11 to 13, and y is 3to 10], and CF 3 (CF 2 CF 2 ) n (CH 2 CH 2 O) y H, where n is 2 to 4 and y is 3 to 10.

11. The method of claim 8 , wherein the surfactant is added in an amount ranging from 0.01 ppm to 1000ppm of the total weight of the composition.

12. The method of claim 1 , wherein forming the second hard mask pattern comprises:
forming a second hard mask layer on the first hard mask layer;
forming a photoresist pattern on the second hard mask layer; and
patterning the second hard mask layer using the photoresist pattern as an etch mask.

13. The method of claim 1 , wherein forming the first hard mask layer comprises:
forming a first sub-hard mask layer to cover an entire surface of the lower structure, the first sub-hard mask layer having a level top surface; and
forming a second sub-hard mask layer on the first sub-hard mask layer.

14. The method of claim 13 , wherein forming the first sub-hard mask layer comprises coating a first composition and curing the first composition; and forming the second sub-hard mask layer comprises coating a second composition and curing the second composition.

15. The method of claim 13 , wherein the first composition includes a first compound of Formula (1) below, and wherein the second composition includes a second compound of Formula (2) below:

wherein in Formula (1), p is an integer ranging from 100 to 3000,R 1 is a methylene or an arylene; R 2 and R 3 are each independently a hydroxyl group, halogen or C 1 to C 19 alkyl group; and R 4 is C 1 -C 19 alkyl group or aromatic cyclic compound, and
wherein in Formula (2), n+m is an integer ranging from 100 to 3000; R 5 is a methylene or an arylene; and R 6 is C 1 -C 19 alkyl group or aromatic cyclic compound.

16. The method of claim 1 , wherein ends of the second etch target layers are formed to have a step formation.

Assignees

• Koh Chawon
• Park Cheol Hong
• Kim Ki-Jeong
• Kim Hyunwoo
• Lee Hyosung
• Samsung Electronics Co Ltd

Inventors

• Koh Chawon
• Park Cheol Hong
• Kim Ki-Jeong
• Kim Hyunwoo
• Lee Hyosung

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P76/20 Primary

  of masks comprising organic materials · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L21/0271 Primary

  Electricity · mapped topic