Nonvolatile memory device and read method thereof

Patent metadata

Field	Value
Publication number	US-9564237-B2
Application number	US-201514946848-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	Nov 14, 2008
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array connected to a plurality of word lines;
a voltage generator for supplying a select read voltage to a select word line, a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line and a second unselect read voltage to remaining unselect word lines in the memory cell array;
an input/output circuit electrically coupled to bit lines associated with the memory cell array; and
a control circuit electrically coupled to said input/output circuit and said voltage generator, said control circuit configured to control said voltage generator so that a level of the first unselect read voltage is set according to an elapsed time of a memory block within the memory cell array to be read after a program of the memory block.

2. The nonvolatile memory device of claim 1 , wherein the level of the first unselect read voltage set by said voltage generator decreases when the elapsed time increases.

3. The nonvolatile memory device of claim 1 , wherein the level of the first unselect read voltage set by said voltage generator increases when the elapsed time increases.

4. The nonvolatile memory device of claim 1 , wherein the memory cell array comprises a plurality of memory blocks and wherein a respective program time associated with each of the plurality of memory blocks is stored within the memory cell array.

5. A read method of a nonvolatile memory device, comprising:
detecting an elapsed time a memory block to be read of the nonvolatile memory device after a program of the memory block;
selecting a level of a first unselect read voltage according to the elapsed time; and
performing a read operation by supplying a select read voltage to a select word line, supplying the first unselect read voltage to at least one between the upper word line and the lower word line adjacent to the select word line and supplying a second unselect read voltage to remaining word lines of the memory block.

Assignees

• Lee Changhyun
• Choi Jungdal
• Choe Byeong-In
• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Choi Jungdal
• Choe Byeong-In

Classifications

• G11C8/10 Primary

  Decoders · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title