Pulse control for non-volatile memory

Patent metadata

Field	Value
Publication number	US-9564225-B2
Application number	US-201514878902-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Mar 24, 2009
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

First claim

We claim:

1. A method of changing state in memory cells of a nonvolatile memory device, where each memory cell has a floating gate, a first conductor and a second conductor, where each memory cell is to store charge on the floating gate according to a potential difference between the first conductor and the second conductor, to indicate a first state in the respective memory cell, and where data is to be programmed or erased in each memory cell using multiple program-verify cycles, each program-verify cycle comprising a program portion and a verify portion, the method comprising:
during the program portion of each program-verify cycle, repeatedly pulsing application of the potential difference between the first conductor and the second conductor, dependent on state of a corresponding bit line, to provide for a pulsed voltage drop across the memory cell dependent on the state of the corresponding bit line; and
for each memory cell to which the pulsed voltage drop is to be provided, between each application of the potential difference, providing for a rest period;
where each pulse of the voltage drop has a duration of no greater than 100 nanoseconds.

2. The method of claim 1 , where the second conductor is a channel and where the method further comprises, responsive to logic state of the corresponding bitline, pulsing the channel between a first voltage and a second voltage.

3. The method of claim 1 , where repeatedly pulsing application of the potential difference comprises using an access transistor under the influence of a pulsed control signal to provide for the pulses of the voltage drop.

4. The method of claim 1 , further comprising reading pulse control information from a register that is dynamically programmable, the pulse control information including at least two of: (a) pulse frequency, (b) duty cycle of pulsed application the potential difference relative to the rest period, and (c) number of pulses to be applied during each program portion.

5. The method of claim 1 , further comprising reading mode information from a register, the mode information comprising a selective one of (i) a high reliability mode, in which a pulsing mechanism is selectively turned on, the pulsing mechanism to provide for the repeated pulsing of application of the potential difference between the first conductor and the second conductor, and (ii) a performance mode, in which the pulsing mechanism is turned off.

6. The method of claim 1 , where repeatedly pulsing application includes repeatedly pulsing the second conductor between a first voltage and a second voltage during the program portion of each program-verify cycle, to thereby apply a plurality of pulses of the voltage drop, each pulse of the voltage drop having a duration of no greater than approximately 50 nanoseconds, the rest period between each adjacent pair of consecutive pulses of the voltage drop in the plurality being at least 500 nanoseconds.

7. The method of claim 6 , where each pulse of the voltage drop has a duration of no greater than approximately 30 nanoseconds, and pulse frequency is no greater than approximately once every 800 nanoseconds.

8. The method of claim 1 , where:
the second conductor comprises a channel coupled to a driver that is under control of the corresponding bitline; and
repeatedly pulsing application comprises pulsing the driver on and off to sequentially generate pulses of the voltage drop during the program portion of each program-verify cycle, each pulse to provide an electrical connection between the channel and a programming voltage; and
the method further comprises coupling multiple drivers to the corresponding bitline and segmenting the corresponding bitline into corresponding segments, each segment to couple a channel for at least one memory cell to the programming voltage.

9. The method of claim 1 , where repeatedly pulsing application includes pulsing application of a programming voltage to a wordline, partitioning the wordline into multiple segments, employing multiple wordline drivers per logical page, at least one wordline driver per segment, and separately driving each the multiple segments.

10. A nonvolatile memory device in which programming of data is to be performed using program-verify cycles for each of plural memory cells, each program-verify cycle having a programming portion and a verify portion, the nonvolatile memory device comprising:
for each of the memory cells, a first conductor, a second conductor, a floating gate between the first conductor and the second conductor, and a bitline; and
a pulsing mechanism to pulse application a voltage drop between the first conductor and the second conductor so as to store charge on the corresponding floating gate according to state of the corresponding bitline;
where, for those memory cells that are to receive pulsed application of the voltage drop according to the state of the corresponding bitline, the non-volatile memory device is to pulse application of the voltage drop repeatedly during each program portion and, in between each adjacent pair of pulses of the voltage drop, is to provide for a rest period; and
where each pulse of the voltage drop has a duration of no greater than 100 nanoseconds.

11. The device of claim 10 , where the device is a flash memory device.

12. The device of claim 11 , where the pulsing mechanism includes an access transistor to control electrical connection of one of a wordline to a current source, or a channel to a current source, the access transistor to repeatedly pulse the electrical connection at a frequency that is no less than once per microsecond.

13. The device of claim 10 , further comprising a register to store at least two of: (a) pulse frequency, (b) duty cycle of the pulse of the voltage drop relative to the rest period, and (c) number of pulses of the voltage drop to be applied during each program portion, the register being dynamically programmable by a remote memory controller.

14. The device of claim 10 , where the device further comprises a register to store a mode setting, including a selective one of a (i) a high reliability mode setting, in which the pulsing mechanism is selectively turned on, and (ii) a performance mode setting, in which the pulsing mechanism is turned off, and where the register is programmable by a remote memory controller to define the mode setting.

15. The device of claim 10 , where each pulse of the voltage drop has a duration of no greater than approximately 50 nanoseconds, and where the rest period between each pair of adjacent pulses of the voltage drop is at least 500 nanoseconds.

16. The device of claim 15 , where each pulse of the voltage drop has a duration of no greater than approximately 30 nanoseconds, and pulse frequency is no greater than approximately once every 800 nanoseconds.

17. The device of claim 10 , where for each memory cell to receive pulsed application of the voltage drop according to the state of the corresponding bitline, the pulsing mechanism is to pulse application of a programming voltage to a wordline.

18. The device of claim 10 , where for each memory cell to receive pulsed application of the voltage drop according to the state of the corresponding bitline, the pulsing mechanism is to pulse a channel between first and second voltage references.

Assignees

• Rambus Inc

Inventors

• Kellam Mark D
• Haukness Brent Steven
• Bronner Gary B
• Donnelly Kevin

Classifications

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title