Command signal management in integrated circuit devices

Patent metadata

Field	Value
Publication number	US-9564222-B2
Application number	US-201514856147-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Apr 11, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

First claim

What is claimed is:

1. A method of operating an integrated circuit device, comprising:
performing an operation on the integrated circuit device responsive, at least in part, to a logic level of a command signal line received at control circuitry of the integrated circuit device;
generating an output signal having a logic level indicating whether the operation is being performed;
logically combining the logic level of the output signal with the logic level of the command signal line to generate a command signal to the control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal has a logic level indicting that the operation is not being performed, and having a particular logic level when the output signal has a logic level indicating that the operation is being performed.

2. The method of claim 1 , wherein generating the output signal having a logic level indicating whether the operation is being performed comprises generating the output signal having a logic level indicating whether the operation is being performed in response to signals received from the control circuitry of the integrated circuit device.

3. The method of claim 1 , wherein performing the operation on the integrated circuit device responsive, at least in part, to a logic level of the command signal line received at control circuitry of the integrated circuit device comprises performing the operation on the integrated circuit device responsive to logic levels of more than one command signal line.

4. The method of claim 1 , wherein logically combining the logic level of the output signal with the logic level of the command signal line comprises providing the logic level of the output signal and the logic level of the command signal line to inputs of an AND gate.

5. The method of claim 1 , wherein generating the output signal having a logic level indicating whether the operation is being performed comprises:
receiving a pattern of logic levels at inputs of an SR latch;
providing an output of the SR latch to a first input of a D latch; and
providing the logic level of the command signal line to a second input of the D latch.

6. The method of claim 5 , further comprising generating the pattern of logic levels responsive to control signals received from the control circuitry of the integrated circuit device.

7. The method of claim 5 , wherein providing the output of the SR latch to the first input of the D latch comprises providing a Q output of the SR latch to a D input of the D latch.

8. The method of claim 7 , wherein providing the logic level of the command signal line to the second input of the D latch comprises providing the logic level of the command signal line to a clock input of the D latch.

9. The method of claim 8 , wherein generating the output signal having a logic level indicating whether the operation is being performed comprises generating the output signal as an inverted logic level of a Q output of the D latch.

10. An integrated circuit device, comprising:
an interface to receive command signals from an external device;
control circuitry to control operations on the integrated circuit device responsive to the command signals and to generate one or more control signals indicative of a desire to block or allow a particular command signal; and
a command signal management circuit to provide a logic level of the particular command signal to the control circuitry when the one or more control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the one or more control signals indicate a desire to block the particular command signal.

11. The integrated circuit device of claim 10 , wherein the control circuitry is configured to generate one or more other control signals indicative of a desire to block or allow one or more other command signals.

12. The integrated circuit device of claim 11 , and for each respective command signal of the one or more other command signals, further comprising:
a separate command signal management circuit to provide a logic level of that respective command signal of the one or more other command signals to the control circuitry when the one or more other control signals indicate a desire to allow that respective command signal, and to provide a particular logic level to the control circuitry when the one or more other control signals indicate a desire to block that respective command signal.

13. The integrated circuit device of claim 10 , wherein the command signal management circuit comprises:
a logic circuit to generate a pattern of logic levels responsive to the one or more control signals indicative of a desire to block or allow the particular command signal;
an SR latch connected to receive the pattern of logic levels at inputs of the SR latch;
a D latch connected to receive an output of the SR latch at a first input and to receive the command signal at a second input; and
a logic gate connected to receive an output of the D latch at a first input and to receive the command signal at a second input.

14. The integrated circuit device of claim 13 , wherein the pattern of logic levels comprises two logic levels, wherein the SR latch is connected to receive the pattern of two logic levels at an S input and an R input, respectively, wherein the D latch is connected to receive a Q output of the SR latch at its first input, and wherein the logic gate is connected to receive an inverted Q output of the D latch at its first input.

15. An integrated circuit device, comprising:
an interface to receive command signals from an external device;
a logic circuit configured to generate a first signal and a second signal indicative of a desire to block or allow propagation of a particular command signal from the interface;
an SR latch having a first input connected to receive the first signal, a second input connected to receive the second signal, and an output;
a D latch having a first input connected to the output of the SR latch, a second input connected to receive the particular command signal from the interface, and an output; and
a logic gate having a first input connected to the output of the D latch, a second input connected to receive the particular command signal from the interface, and an output;
wherein the logic gate is configured to provide a logic level of the particular command signal at its output when the output of the D latch has a first logic level, and to provide a particular logic level at its output when the output of the D latch has a second logic level different than the first logic level.

16. The integrated circuit device of claim 15 , wherein the output of the D latch is an inverted output.

17. The integrated circuit device of claim 16 , wherein the inverted output of the D latch is an inverted Q output.

18. The integrated circuit device of claim 17 , wherein the first input of the D latch is a D input and the second input of the D latch is a clock input.

19. The integrated circuit device of claim 18 , wherein the logic gate is an AND gate.

20. The integrated circuit device of claim 19 , wherein the output of the SR latch is a Q output.

Assignees

• Micron Technology Inc

Inventors

• Hendrickson Nicholas

Classifications

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title