Current based detection and recording of memory hole-interconnect spacing defects

Patent metadata

Field	Value
Publication number	US-9564219-B2
Application number	US-201514681627-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 8, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.

First claim

It is claimed:

1. In a non-volatile flash memory circuit having an array of memory cells formed according to a NAND type of architecture, a method of determining NAND strings of a block of the array having slow to program memory cells, the memory cells of the NAND strings being formed along word lines and each of the NAND strings of the block connected along a corresponding bit line, the method comprising:
performing a first write operation for a first set of memory cells of the block along a first word line corresponding to a first set of a plurality bit lines, but not for a second set of one or more memory cells of the block along the first word line corresponding to a second set of one or more bit lines, where the second set of bit lines is distinct from the first set of bit lines;
determining an amount of current through the first set of memory cells during the first write operation;
performing a second write operation for the second set of memory cells, but not for the first set of memory cells;
determining an amount of current through the second set of memory cells during the second write operation;
performing a comparison of the amount of current through the first set of memory cells during the first write operation with the amount of current through the second set of memory cells during the second write operation; and
based upon the comparison, performing a determination of whether NAND strings corresponding to the second set of bit lines include memory cells that are slow to program.

2. The method of claim 1 , wherein the amounts of current are the amounts of current during verify operations of the write operations.

3. The method of claim 1 , wherein the determination of whether NAND strings corresponding to the second set of bit lines include memory cells that are slow to program includes determining that the amount of current through the second set of memory during the second write operation exceeds the amount of current through the first set of memory during the first write operation by a first amount.

4. The method of claim 3 , wherein the first amount is a settable parameter.

5. The method of claim 1 , further comprising:
in response to determining that NAND strings corresponding to the second set of bit lines include memory cells that are slow to program, recording the NAND strings corresponding to the second set of bit lines in a record of NAND strings with slow to program memory cells.

6. The method of claim 5 , wherein the record of NAND strings with slow to program memory cells includes entries for all blocks of the array with an indication of whether NAND strings with slow to program memory cells thereof are slow to program or not.

7. The method of claim 5 , wherein the record of NAND strings with slow to program memory cells includes entries for only for blocks of the array with NAND strings with slow to program memory cells.

8. The method of claim 1 , wherein the memory circuit is a monolithic three-dimensional semiconductor memory device having the memory cells arranged in multiple physical levels above a silicon substrate and comprising a charge storage medium, wherein the NAND strings run in a vertical direction relative to the substrate and are formed in groups between local interconnect lines that also run in the vertical direction relative to the substrate, and wherein the bit lines and word lines run in a horizontal direction relative to the substrate,
wherein second set of bit lines are connected to NAND strings adjacent to one or more of the local interconnect lines and the first set of bit lines are connected to NAND strings not adjacent to the local interconnect lines.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Magia Sagar
• Sabde Jagdish
• Pachamuthu Jayavel
• Babariya Ankitkumar

Classifications

• G11C16/32

  Timing circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title