Non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite

Patent metadata

Field	Value
Publication number	US-9564209-B1
Application number	US-201514860763-A
Country	US
Kind code	B1
Filing date	Sep 22, 2015
Priority date	Sep 22, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.

First claim

What is claimed is:

1. A non-volatile static random access memory cell, comprising:
a first inverter, having a first input node and a first output node, voltage supplied by a first differential supply, wherein the first inverter comprises:
a first pull-up transistor having a source terminal coupled to a first high voltage;
a first pull-down transistor having a source terminal coupled to a first low voltage, the first pull-down transistor having a drain terminal coupled to a drain terminal of the first pull-up transistor to form the first output node, wherein the difference between the first high voltage and the first low voltage is the first differential supply;

a second inverter, having a second input node and a second output node, voltage supplied by a second differential supply, wherein the first input node is coupled to the second output node, the second input node is coupled to the first output node, wherein the second inverter comprises:
a second pull-up transistor having a source terminal coupled to a second high supply voltage;
a second pull-down transistor having a source terminal coupled to a second low voltage supply, the second pull-down transistor having a drain terminal coupled to a drain terminal of the second pull-up transistor to form the second output node, wherein the difference between the second high voltage and the second low voltage is the second differential supply;

a first access transistor having a gate terminal coupled to a first word line, the first access transistor having a source terminal coupled to the first output node;
a second access transistor having a gate terminal coupled to the first word line, the second access transistor having a source terminal coupled to the second output node; and
a variable resistive element coupling with a third access transistor in series, directly coupled between the first output node and the second output node;
wherein the non-volatile static random access memory cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase, during the dual supply initialization phase the first high voltage raises before the second high voltage while the first low voltage is the same as the second low voltage and the first output node is initialized as logic “1”, during the pulse-overwrite phase the third access transistor is turned on for a switch period in order to discharge the first output node.

2. The non-volatile static random access memory cell according to claim 1 , wherein when the non-volatile static random access memory cell operates in a store operation the third access transistor is turned on, when the logic value of the first output node is “0” and the logic value of the second output node is “1” the variable resistive element is set to a low resistance state (LRS), when the logic value of the first output node is “1” and the logic value of the second output node is “0” the variable resistive element is set to a high resistance state (HRS).

3. The non-volatile static random access memory cell according to claim 1 , wherein during the pulse-overwrite phase, when the variable resistive element is at a high resistance state (HRS) the first output node is maintained at logic value “1”; wherein during the pulse-overwrite phase, when the variable resistive element is at a low resistance state (LRS) the first output node and the second output node are conducted together due to turning on of the third access transistor, then after the switch period the first output node is changed to logic value “0”, and the second output node is changed to logic value “1”.

4. The non-volatile static random access memory cell according to claim 1 , wherein during the pulse-overwrite phase the first low voltage and the second low voltage are at a ground voltage, the second high voltage is higher than the first high voltage.

5. A non-volatile static random access memory cell, comprising:
a first inverter, having a first input node and a first output node, voltage supplied by a first differential supply, wherein the first inverter comprises:
a first pull-up transistor having a source terminal coupled to a first high voltage;
a first pull-down transistor having a source terminal coupled to a first low voltage, the first pull-down transistor having a drain terminal coupled to a drain terminal of the first pull-up transistor to form the first output node, wherein the difference between the first high voltage and the first low voltage is the first differential supply;

a second inverter, having a second input node and a second output node, voltage supplied by a second differential supply, wherein the first input node is coupled to the second output node, the second input node is coupled to the first output node, wherein the second inverter comprises:
a second pull-up transistor having a source terminal coupled to a second high supply voltage;
a second pull-down transistor having a source terminal coupled to a second low voltage supply, the second pull-down transistor having a drain terminal coupled to a drain terminal of the second pull-up transistor to form the second output node, wherein the difference between the second high voltage and the second low voltage is the second differential supply;

a first access transistor having a gate terminal coupled to a first word line, the first access transistor having a source terminal coupled to the first output node;
a second access transistor having a gate terminal coupled to the first word line, the second access transistor having a source terminal coupled to the second output node; and
a variable resistive element coupling with a third access transistor in series, directly coupled between the first output node and the second output node;
wherein the non-volatile static random access memory cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase, during the dual supply initialization phase the second low voltage is pull-down to a ground voltage before the first low voltage is pull-down to the ground voltage while the first high voltage is the same as the second high voltage and the first output node is initialized as logic “1”, during the pulse-overwrite phase the third access transistor is turned on for a switch period in order to discharge the first output node.

6. A non-volatile static random access memory cell, comprising:
a first inverter, having a first input node and a first output node, voltage supplied by a first differential supply, wherein the first inverter comprises:
a first inverter, having a first input node and a first output node, voltage supplied by a first differential supply, wherein the first inverter comprises:
a first pull-up transistor having a source terminal coupled to a first high voltage;
a first pull-down transistor having a source terminal coupled to a first low voltage, the first pull-down transistor having a drain terminal coupled to a drain terminal of the first pull-up transistor to form the first output node, wherein the difference between the first high voltage and the first low voltage is the first differential supply;

a second inverter, having a second input node and a second output node, voltage supplied by a second differential supply, wherein the first input node is coupled to the second output node, the second input node is coupled to the first output node, wherein the second inverter comprises:
a second pull-up transistor having a source terminal coupled to a second high supply voltage;
a second pull-down transistor having a source terminal coupled to a second low voltage supply, the second pull-down transistor having a drain terminal coupled to a drain terminal of the second pull-up transistor to form the second output node, wherein the difference between t

Assignees

• Nat Univ Tsing Hua

Inventors

• Lee Albert
• Lin Chien-Chen
• Lo Chieh-Pu
• Chang Meng-Fan

Classifications

• G11C14/009 Primary

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title