Clock verification

Patent metadata

Field	Value
Publication number	US-9563727-B2
Application number	US-201514674555-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

First claim

The invention claimed is:

1. A method of verifying a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the hardware design from a reference clock signal to have a particular duty cycle and period, the method comprising:
counting, by at least one first state machine, a number of full or half cycles of a first clock signal that occur between a rising edge and a falling edge of a second clock signal, the second clock signal operating at a lower frequency than the first clock signal, wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal;
counting, by at least one second state machine, a number of full or half cycles of the first clock signal that occur between a falling edge and a rising edge of the second clock signal;
receiving counts from said at least one first and second state machines;
verifying the duty cycle and the period of the derived clock signal by evaluating one or more assertions written in an assertion-based language that compare the received counts from said at least one first and second state machines to one or more predetermined numbers; and
manufacturing an integrated circuit in accordance with the integrated circuit hardware design having the verified function.

2. The method of claim 1 , wherein counting the number of full cycles of the first clock signal that occur between two edges of the second clock signal comprises counting the number of rising edges of the first clock signal that occur between the two edges of the second clock signal.

3. The method of claim 1 , wherein counting the number of half cycles of the first clock signal that occur between two edges of the second clock signal comprises:
counting the number of rising edges of the first clock signal that occur between the two edges of the second clock signal;
counting the number of falling edges of the first clock signal that occur between the two edges of the second clock signal; and
summing the number of rising edges and the number of falling edges to produce the number of half cycles of the first clock signal that occur between the two edges of the second clock signal.

4. The method of claim 1 , wherein the one or more assertions comprise an assertion that when the second clock signal falls from a high value to a low value the count of half cycles or full cycles of the first clock signal that occur between the rising edge and falling edge of the second clock signal is equal to one of the one or more predetermined numbers.

5. The method of claim 1 , wherein the one or more assertions comprise an assertion that when the second clock signal rises from a low value to a high value the count of half cycles or full cycles of the first clock signal that occur between the falling edge and the rising edge of the second clock signal is equal to one of the one or more predetermined numbers.

6. The method of claim 1 , wherein the first clock signal is derived from the second clock signal through multiplication.

7. The method of claim 1 , wherein the second clock signal is derived from the first clock signal through division.

8. The method of claim 1 , wherein at least one of the first clock signal and the second clock signal has a variable duty cycle.

9. A system to verify a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the hardware design from a reference clock signal to have a particular duty cycle and period, the system comprising:
at least one first state machine configured to count a number of full or half cycles of a first clock signal that occur between a rising edge and a falling edge of a second clock signal, the second clock signal operating at a lower frequency than the first clock signal, wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal;
at least one second state machine configured to count a number of full or half cycles of the first clock signal that occur between a falling edge and a rising edge of the second clock signal; and
an assertion verification unit configured to verify the duty cycle and period of the derived clock signal by evaluating one or more assertions written in an assertion-based language that compare the counts from said at least one first and second state machines to one or more predetermined numbers;
wherein the system is configured to implement a manufacturing process to manufacture an integrated circuit in accordance with the integrated circuit hardware design having the verified function.

10. The system of claim 9 , wherein the at least one first state machine comprises a state machine configured to count the number of rising edges of the first clock signal that occur between the rising edge and the falling edge of the second clock signal; and the at least one second state machine comprises a state machine configured to count the number of rising edges of the first clock signal that occur between the falling edge and the rising edge of the second clock signal.

11. The system of claim 10 , wherein the at least one first state machine further comprises another state machine configured to count the number of falling edges of the first clock signal that occur between the rising edge and the falling edge of the second clock signal, and a further state machine configured to sum the number of rising edges and falling edges of the first clock signal that occur between the rising edge and the falling edge of the second clock signal to produce the number of half cycles of the first clock signal that occur between the rising edge and the falling edge of the second clock signal; and
the at least one second state machine further comprises another state machine configured to count the number of falling edges of the first clock signal that occur between the falling edge and the rising edge of the second clock signal, and a further state machine configured to sum the number of rising edges and falling edges of the first clock signal that occur between the falling edge and the rising edge of the second clock signal to produce the number of half cycles of the first clock signal that occur between the falling edge and the rising edge of the second clock signal.

12. The system of claim 9 , wherein the one or more assertions comprises two assertions written in an assertion-based language.

13. The system of claim 9 , wherein the one or more assertions comprise an assertion that when the second clock signal falls from a high value to a low value the count of half cycles or full cycles of the first clock signal that occur between the rising edge and falling edge of the second clock signal is equal to one of the one or more predetermined numbers.

14. The system of claim 9 , wherein the one or more assertions comprise an assertion that when the second clock signal rises from a low value to a high value the count of half cycles or full cycles of the first clock signal that occur between the falling edge and the rising edge of the second clock signal is equal to one of the one or more predetermined numbers.

15. The system of claim 9 , wherein the first clock signal is derived from the second clock signal through multiplication.

16. The system of claim 9 , wherein the second clock signal is derived from the first clock sig

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G01R31/31727 Primary

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title