Storage control device and method of controlling storage control device

US9563574B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9563574-B2
Application numberUS-201314760303-A
CountryUS
Kind codeB2
Filing dateFeb 12, 2013
Priority dateFeb 12, 2013
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To improve response performance of a storage control device. A storage control device 1 connected to a host computer 2 includes: a communication unit 1 A that receives a command, to which a priority is set, from the host computer; a command executing unit 1 B that executes the command received from the communication unit according to the priority; a cache memory 1 C that is used by the command executing unit; a cache controller 1 E that manages slots of the cache memory; and a plurality of storage devices 1 D( 1 ) and 1 D( 2 ) that stores data used by the host computer. The cache controller sets the priority to a slot that stores target data of the command and controls the data stored in the slot according to the priority.

First claim

Opening claim text (preview).

The invention claimed is: 1. A storage control device connected to a host computer, comprising: a communication unit that receives a command, to which a priority is set, from the host computer; a command executing unit that executes the command received from the communication unit according to the priority; a cache memory that is used by the command executing unit; a cache controller that manages slots of the cache memory; and a plurality of storage devices that stores data used by the host computer, including a high speed storage device whose response speed is high and a low speed storage device whose response speed is low, wherein the cache controller sets the priority to a slot that stores target data of the command and controls the data to allocate slots for each priority by using a target slot count that is set for each priority as a target value, so that data whose priority is high stay in the cache memory a long time, and distributes the target slot count that is set for each priority to the high speed storage device and the low speed storage device inversely proportional to the response speed. 2. The storage control device according to claim 1 , wherein the cache controller sets the target slot count based on a target response time that is set for each priority. 3. The storage control device according to claim 2 , wherein the cache controller controls the target slot count based on a difference between an actual response time required for processing the command and the target response time set for the slot that stores the target data. 4. The storage control device according to claim 3 , wherein when a new command, under which the data stored in a slot is targeted, is received, the cache controller compares a priority of the new command with a priority set to the data stored in the slot and uses the higher priority as the priority of the data stored in the slot. 5. The storage control device according to claim 1 , wherein the cache controller performs control so that data, the non-used time of which is longest and which is stored in a predetermined slot having the lowest priority is discarded first. 6. The storage control device according to claim 5 , wherein when the number of slots allocated to a priority that is set to the predetermined slot exceeds a predetermined value, the cache controller discards data stored in the predetermined slot. 7. The storage control device according to claim 1 , further comprising: a host-side communication device connected to the host computer so as to accomplish implementation of the communication unit; a drive-side communication device connected to the plurality of storage devices; a cache memory device having the cache memory; and a microprocessor device connected to the host-side communication device, the drive-side communication device, the cache memory device, and the management communication device, wherein the microprocessor device includes: a plurality of command executing units; a memory unit that is shared by the plurality of command executing units; a first queue provided in the memory unit so as to manage an execution sequence of commands; a second queue provided in the memory unit so as to discard data according to the priority that is set to each slot; and a management table provided in the memory unit so as to manage the priority for each slot and a type of a destination storage device after associating the priority with the type, a command executing unit that executes the commands among the plurality of command executing units executes the commands according to the priority using the first queue, and the cache controller is configured such that: the priority set to the command is set to a slot that stores the target data of the command; the priority set to the slot that stores the target data and the type of whether a storage device, which is the storage destination of the target data, is the high speed storage device or the low speed storage device are set in the management table; a target slot count for each priority is set based on a target response time that is set such that the higher the priority the shorter the target response time and the type of the destination storage device; slots are allocated to each of the plurality of priorities so that the larger the number of slots becomes the higher the priority is set by using the target slot count as a target value; the target slot count is controlled based on a difference between an actual response time required for the command executing unit to process the command and the target response time set to a slot that stores the target data, so that the target slot count is decreased when the actual response time is shorter than the target response time and the target slot count is increased when the actual response time is longer than the target response time; when a new command, under which the data stored in a slot is target, is received, the priority of the new command is compared with the priority set to the target data stored in the slot, and the higher priority is used as the priority of the target data stored in the slot; and data the non-used time of which is longest and which is stored in a predetermined slot having the lowest priority is discarded is discarded when the number of slots allocated to the priority that is set to the predetermined slot exceeds a predetermined value.

Assignees

Inventors

Classifications

  • with priority control · CPC title

  • Allocation or management of cache space · CPC title

  • G06F12/122Primary

    of the least frequently used [LFU] type, e.g. with individual count value · CPC title

  • Details relating to cache allocation · CPC title

  • Control mechanisms for virtual memory, cache or TLB · CPC title

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What does patent US9563574B2 cover?
To improve response performance of a storage control device. A storage control device 1 connected to a host computer 2 includes: a communication unit 1 A that receives a command, to which a priority is set, from the host computer; a command executing unit 1 B that executes the command received from the communication unit according to the priority; a cache memory 1 C that is used by the c…
Who is the assignee on this patent?
Hitachi Ltd
What technology area does this patent fall under?
Primary CPC classification G06F12/0871. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).