Debugger display of vector register contents after compiler optimizations for vector instructions

Patent metadata

Field	Value
Publication number	US-9563534-B1
Application number	US-201514850652-A
Country	US
Kind code	B1
Filing date	Sep 10, 2015
Priority date	Sep 4, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code. The compiler generates a debugger table that specifies which instructions have corresponding reformatting operations. A debugger then uses the debugger table to display contents of the vector register, which is displayed in regular form as well as in a form that is reformatted according to information in the debugger table.

First claim

The invention claimed is:

1. An apparatus comprising:
at least one processor;
a memory coupled to the at least one processor;
a computer program residing in the memory, the computer program including a plurality of instructions that includes at least one vector instruction;
a debug table that specifies a vector register, a corresponding address range for the specified vector register, and a corresponding endian reformatting type for the specified vector register; and
a debugger residing in the memory and executed by the at least one processor, the debugger receiving a request to display contents of a vector register at a current instruction in the computer program, and in response, the debugger determines whether the current instruction has an address within an address range in the debug table, and when the current instruction is not within an address range in the debug table, the debugger displays the contents of the vector register, and when the current instruction has an address within an address range of the debug table, the debugger determines from the debug table an endian reformatting type corresponding to the address range, and displays the contents of the vector register and additionally displays the contents of the vector register after reformatting the contents according to the endian reformatting type.

2. The apparatus of claim 1 further comprising a compiler that generates the debug table during compilation of the computer program.

3. The apparatus of claim 2 wherein the compiler generates the debug table during compilation of the computer program by annotating instructions in the computer program that are in an address range corresponding to a vector reformatting operation.

4. The apparatus of claim 1 wherein the debug table comprises a plurality of entries, each entry including:
a vector register;
a start address;
an end address; and
an endian reformatting type.

5. The apparatus of claim 1 wherein the endian reformatting type comprises a swap.

6. The apparatus of claim 1 wherein the endian reformatting type includes at least one instruction to undo endian reformatting done by a compiler.

7. An apparatus comprising:
at least one processor;
a memory coupled to the at least one processor;
a computer program residing in the memory, the computer program including a plurality of instructions that includes at least one vector instruction;
a debug table that comprises a plurality of entries, each entry including:
a vector register;
a start address;
an end address; and
an endian reformatting type;

a compiler that generates the debug table during compilation of the computer program by annotating instructions in the computer program that are in an address range corresponding to an endian vector reformatting operation; and
a debugger residing in the memory and executed by the at least one processor, the debugger receiving a request to display contents of a vector register at a current instruction in the computer program, and in response, the debugger determines whether the current instruction has an address within an address range in the debug table, and when the current instruction is not within an address range in the debug table, the debugger displays the contents of the vector register, and when the current instruction has an address within an address range of the debug table, the debugger determines from the debug table an endian reformatting type corresponding to the address range, and displays the contents of the vector register and additionally displays the contents of the vector register after reformatting the contents according to the endian reformatting type.

8. The apparatus of claim 7 wherein the endian reformatting type comprises a swap.

9. The apparatus of claim 7 wherein the endian reformatting type includes at least one instruction to undo endian reformatting done by the compiler.

10. An article of manufacture comprising software stored on a computer readable storage medium, the software comprising:
a debug table that specifies a vector register, a corresponding address range for the specified vector register, and a corresponding endian reformatting type for the specified vector register; and
a debugger receiving a request to display contents of a vector register at a current instruction in a computer program that includes a plurality of instructions that includes at least one vector instruction, and in response, the debugger determines whether the current instruction has an address within an address range in the debug table, and when the current instruction is not within an address range in the debug table, the debugger displays the contents of the vector register, and when the current instruction has an address within an address range of the debug table, the debugger determines from the debug table an endian reformatting type corresponding to the address range, and displays the contents of the vector register and additionally displays the contents of the vector register after reformatting the contents according to the endian reformatting type.

11. The article of manufacture of claim 10 further comprising a compiler that generates the debug table during compilation of the computer program.

12. The article of manufacture of claim 11 wherein the compiler generates the debug table during compilation of the computer program by annotating instructions in the computer program that are in an address range corresponding to a vector reformatting operation.

13. The article of manufacture of claim 10 wherein the debug table comprises a plurality of entries, each entry including:
a vector register;
a start address;
an end address; and
an endian reformatting type.

14. The article of manufacture of claim 10 wherein the endian reformatting type comprises a swap.

15. The article of manufacture of claim 10 wherein the endian reformatting type includes at least one instruction to undo endian reformatting done by a compiler.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Schmidt William J

Classifications

• G06F11/3624 Primary

  by performing operations on the source code, e.g. via a compiler · CPC title

• G06F11/362

  Debugging of software · CPC title

• G06F11/36 Primary

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F11/3698

  Environments for analysis, debugging or testing of software · CPC title