Storage integrity validator

US9563500B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9563500-B2
Application numberUS-201615068688-A
CountryUS
Kind codeB2
Filing dateMar 14, 2016
Priority dateMay 31, 2013
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A sequence code verification system can be designed to include a data reader, a validity engine, and an error notifier. The data reader can read sequence codes from consecutive logical blocks. The validity engine can invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier can notify a user of an error for each invalidated write operation batch. The system can validate data written to logical blocks on a storage subsystem adapted so that, during write operations, an additional sequence code is written to each logical block of data. The sequence code can remain constant for each write operation batch and the sequence code can be incremented for each new write operation batch.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for validating data written to logical blocks on a storage subsystem, said storage subsystem being adapted so that during write operations of data to logical blocks, an additional sequence code is written to each logical block whereby said sequence code remains constant for each write operation batch and whereby said sequence code is incremented for each new write operation batch, each sequence code being an eight byte value that is written to a part of the logical block that is reserved for application data, said method comprising: (A) reading respective first and second sequence codes (S(n) and S(n+1)) from consecutive first and second logical blocks (L(n) and L(n+1)); (B) checking validity by applying the following operations: (1) invalidating a corresponding write operation batch if a first sequence code (S(n)) is less than the second sequence code (S(n+1)) and a block offset (F(n+1)) of the second logical block (L(n+1)) is not equal to zero; (2) invalidating the corresponding write operation batch if the first sequence number (S(n)) is more than the second sequence number (S(n+1)) and a block offset F(n) of a first block (L(n)) does not correspond to the number of logical blocks in a corresponding batch write operation for a first logical block (L(n)); the block offset F(n) of the first logical block (L(n)) equaling the number of logical blocks in the batch write operation minus one; (C) notifying an error for each invalidated write operation batch; performing steps (A), (B) and (C) for each logical block (n) from a plurality of logical blocks (zero to N); and (D) ensuring that a first thread places a reservation in the storage subsystem for those logical blocks that it is going to write to, before it obtains the sequence number it will use in the write. 2. The method of claim 1 wherein checking validity by applying a further test of validating the logical block pair (n and n+1) if a torn write occurs at logical block L(n) where block offset F(n) modulus of a predetermined verification system block offset is zero.

Assignees

Inventors

Classifications

  • Single storage device · CPC title

  • in relation to data integrity, e.g. data losses, bit errors · CPC title

  • in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

  • Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

  • Management of blocks · CPC title

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What does patent US9563500B2 cover?
A sequence code verification system can be designed to include a data reader, a validity engine, and an error notifier. The data reader can read sequence codes from consecutive logical blocks. The validity engine can invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifie…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F11/0727. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).