Apparatus and method for activating and shutting down individual enhanced pipeline stages based on stage priority and performance requirements

Patent metadata

Field	Value
Publication number	US-9563259-B2
Application number	US-35791009-A
Country	US
Kind code	B2
Filing date	Jan 22, 2009
Priority date	Jan 25, 2008
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

First claim

The invention claimed is:

1. A pipeline-based processor, comprising:
at least one pipeline, the at least one pipeline at least including a particular pipeline, wherein the particular pipeline is partitioned into one or more base pipeline stages and a plurality of enhanced pipeline stages based on one or more functions, each of the one or more base pipeline stages being activated while the particular pipeline is activated, each enhanced pipeline stage of the plurality of enhanced pipeline stages having a particular priority level of at least two priority levels, at least one of the plurality of enhanced pipeline stages having a different priority level than at least one other of the plurality of enhanced pipeline stages, the at least two priority levels including at least a highest priority level, the highest priority level having a relative priority higher than any other priority level of the at least two priority levels, the particular priority level of each enhanced pipeline stage of the plurality of enhanced pipeline stages stored in a memory means of the pipeline-based processor; and
a controller circuit, the controller circuit being configured to activate or shut down each enhanced pipeline stage of the plurality of enhanced pipeline stages based on the particular priority level of a corresponding particular enhanced pipeline stage and requirements for performance of a workload, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage, all functions of each shutdown enhanced pipeline stage being not activated, at least one function of each activated enhanced pipeline stage being activated, wherein at least one of the plurality of enhanced pipeline stages is configured to be activated while at least another of the plurality of enhanced pipeline stages is shut down.

2. The pipeline-based processor of claim 1 ,
wherein each priority level is determined according to a performance-to-power consumption ratio of a particular enhanced pipeline stage, wherein a relatively high performance-to-power consumption ratio corresponds to a relatively high priority level.

3. The pipeline-based processor of claim 2 , wherein the controller circuit is configured to activate at least two of the plurality of enhanced pipeline stages in a high-to-low order of the at least two priority levels when the workload increases.

4. The pipeline-based processor of claim 2 , wherein the controller circuit is configured to shut down at least two of the plurality of enhanced pipeline stages in a low-to-high order of the at least two priority levels when the workload decreases.

5. The pipeline-based processor of claim 1 , wherein the particular priority level of each enhanced pipeline stage is based upon a performance-to-power consumption ratio.

6. The pipeline-based processor of claim 1 , wherein a particular enhanced pipeline stage having the highest priority level has a higher performance-to-power consumption ratio than any other enhanced pipeline stage having a priority level other than the highest priority level.

7. The pipeline-based processor of claim 1 ,
wherein a given pipeline stage of the one or more base pipeline stages or the plurality of enhanced pipeline stages includes at least one base module and a plurality of enhanced modules, each of the at least one base module of the given pipeline stage being activated while the given pipeline stage is activated, and
wherein the controller circuit is further configured to:
activate or shut down each enhanced module of the plurality of enhanced modules.

8. A pipeline-based processor, comprising:
at least one pipeline, the at least one pipeline at least including a particular pipeline, wherein the particular pipeline is partitioned into a plurality of pipeline stages based on one or more functions, the plurality of pipeline stages including one or more base pipeline stages and a plurality of enhanced pipeline stages, each of the one or more base pipeline stages being activated while the particular pipeline is activated, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage, all functions of each shutdown enhanced pipeline stage being not activated, at least one function of each activated enhanced pipeline stage being activated, wherein at least one of the plurality of enhanced pipeline stages is configured to be activated while at least another of the plurality of enhanced pipeline stages is shut down, each enhanced pipeline stage of the plurality of enhanced pipeline stages having a particular priority level of at least two priority levels, at least one of the plurality of enhanced pipeline stages having a different priority level than at least one other of the plurality of enhanced pipeline stages, the at least two priority levels including at least a highest priority level, the highest priority level having a relative priority higher than any other priority level of the at least two priority levels, the particular priority level of each enhanced pipeline stage of the plurality of enhanced pipeline stages stored in a memory means of the pipeline-based processor, a particular pipeline stage of the one or more base pipeline stages or the plurality of enhanced pipeline stages including at least one base module and a plurality of enhanced modules, each of the at least one base module of the particular pipeline stage being activated while the particular pipeline stage is activated; and
a controller circuit, the controller circuit being configured to:
activate or shut down each enhanced pipeline stage of the plurality of enhanced pipeline stages based on the particular priority level of a corresponding particular enhanced pipeline stage and requirements for performance of a workload; and
activate or shut down each enhanced module of the plurality of enhanced modules based on the requirements for performance of the workload.

9. The pipeline-based processor of claim 8 , wherein each enhanced module has a particular module priority level of at least two module priority levels, at least one of the plurality of enhanced modules having a different module priority level than at least one other of the plurality of enhanced modules, the at least two module priority levels including at least a highest module priority level, the highest module priority level having a relative priority higher than any other module priority level of the at least two module priority levels, and
wherein the controller circuit being configured to activate or shut down each enhanced module of the plurality of enhanced modules based on the requirements for performance of the workload further comprises the controller circuit being configured to:
activate or shut down each enhanced module of the plurality of enhanced modules based on the particular module priority level of a particular corresponding enhanced module and requirements for performance of a workload.

10. The pipeline-based processor of claim 8 , wherein a base module of a particular base pipeline stage comprises a module that executes a smallest function of the particular base pipeline stage.

11. The pipeline-based processor of claim 8 , wherein an enhanced module of a particular base pipeline stage comprises a module that enhances one or more functions of the particular base pipeline stage.

12. The pipeline-based processor of claim 8 , wherein a base module of a given enhanced pipeline stage comprises a module that enables data to pass through the given enhanced pipeline stage without being changed.

13. A method for a pipeline-based processor, wherein the pipeline-based

Assignees

• Shen Wen Bo
• Shao Peng
• Li Yu
• Chang Xiao Tao
• Ge Yi
• Wang Huayong
• Zou Huan Hao
• IBM

Inventors

• Shen Wen Bo
• Shao Peng
• Li Yu
• Chang Xiao Tao
• Ge Yi
• Wang Huayong
• Zou Huan Hao

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F11/30

  Monitoring · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title