Modifying a scan chain for improved fault diagnosis of integrated circuits

Patent metadata

Field	Value
Publication number	US-9562945-B2
Application number	US-201615097778-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Apr 27, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A computer program product for implementing a scan chain to test a semiconductor including one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions including: program instructions to obtain an initial structure of the scan chain, program instructions to determine, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency, program instructions to adjust the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency, and program instructions to determine a key subset of a fan-out scan register in the at least one scan register pair with backward dependency.

First claim

The invention claimed is:

1. A computer program product for implementing a scan chain to test a semiconductor, the computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer to cause the computer to perform a method comprising:
obtaining, by the computer, an initial structure of the scan chain;
determining, by the computer, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency; and
adjusting, by the computer, the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency; and
determining, by the computer, a key subset of a fan-out scan register in the at least one scan register pair with backward dependency, wherein a fan-in scan register in the at least one scan register pair with backward dependency belongs to the key subset of the fan-out scan register,
wherein logic values of all fan-in scan registers in the key subset of the fan-out scan register and a logic value of an output of a function module connected to the fan-out scan register are the same, no matter which logic values are taken by fan-in scan registers outside the key subset of the fan-out scan register.

2. The computer program product according to claim 1 , wherein excluding any fan-in scan register from the key subset of the fan-out scan register will result in a new subset of fan-out scan registers formed by the remaining fan-in scan registers that do not conform to a definition of the key subset of the fan-out scan register.

3. The computer program product according to claim 1 , wherein obtaining, by the computer, the key subset of the fan-out scan register in the at least one scan register pair with backward dependency comprises:
determining, by the computer, the key subset of the fan-out scan register by a signal tracing method.

4. The computer program product according to claim 1 , wherein determining, by the computer, the key subset of the fan-out scan register in the at least one scan register pair with backward dependency comprises:
determining, by the computer, the key subset of the fan-out scan register by an enumeration method.

Assignees

• IBM

Inventors

• Chen Liang
• Jiang Guofan
• Lin Teng
• Liu Yang

Classifications

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/3172 Primary

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title

• G01R31/318583 Primary

  Design for test · CPC title