Handheld imaging device with VLIW image processor

Patent metadata

Field	Value
Publication number	US-9560221-B2
Application number	US-201213620977-A
Country	US
Kind code	B2
Filing date	Sep 15, 2012
Priority date	Jul 15, 1997
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A handheld imaging device includes an image sensor for sensing an image: a Very Long Instruction Word (VLIW) processor for processing the sensed image; a plurality of processing units provided in the VLIW processor, the plurality of processing units connected in parallel by a crossbar switch to form a multi-core processing unit for the VLIW processor; and an image sensor interface for receiving signals from the image sensor and converting the signals to a format readable by the VLIW processor, the image sensor interface sharing a wafer substrate with the VLIW processor. A transfer of data from the image sensor interface to the VLIW processor is conducted entirely on the shared wafer substrate.

First claim

I claim:

1. A portable imaging device, comprising:
an image sensor configured to generate signals carrying data relating to an image sensed by the image sensor;
a Very Long Instruction Word (VLIW) processor for processing the data relating to the image sensed by the image sensor;
a plurality of processing units provided in the VLIW processor, the plurality of processing units connected in parallel by an interface to form a multi-core processing unit for the VLIW processor;
an image sensor interface for receiving the signals from the image sensor and converting the signals to a format readable by the VLIW processor, the image sensor interface sharing a wafer substrate with the VLIW processor;
an input buffer provided on the shared wafer substrate and in communication with the multi-core processing unit wherein the input buffer is configured to receive input from the image sensor interface; and
a connection coupling the input buffer to the multi-core processing unit, wherein:
a transfer of data from the image sensor interface to the VLIW processor is conducted entirely on the shared wafer substrate, and
the connection is separate from the interface connecting the plurality of processing units in parallel.

2. The device according to claim 1 , wherein the input buffer is configured for receiving data bound for the plurality of processing units and configured for sharing by each of the plurality of processing units.

3. The device according to claim 1 , further comprising an output buffer provided on the shared wafer substrate and in communication with the multi-core processing unit, the output buffer for receiving data processed by the plurality of processing units and configured for sharing by each of the plurality of processing units.

4. The device according to claim 3 , further comprising a print head interface, the print head interface for reading dither-formatted data from the output buffer and passing the dither-formatted data to a print head.

5. The device according to claim 1 , further comprising a scanner for scanning for a presence of a pattern.

6. The device according to claim 5 , further comprising a scanner interface for receiving from the scanner data indicative of the presence of the pattern, and decoding the pattern into an image processing script.

7. The device according to claim 6 , further comprising a CPU for executing an image processing language interpreter on the image processing script, and providing instructions to the VLIW processor to process the data relating to the image sensed by the image sensor in accordance with the image processing script.

8. The device according to claim 1 , wherein the image sensor is a charge-coupled device (CCD), and the image sensor interface includes an analogue/digital converter for converting signals passing between the processor and the CCD.

9. The device according to claim 1 , further comprising a data cache connected to the plurality of processing units via a plurality of buses.

10. The device according to claim 9 , wherein each of the plurality of processing units includes two I/O address generators, and each I/O address generator is connected to a respective one of the plurality of buses.

11. The device according to claim 10 , further comprising an external memory configured to store the data relating to the image sensed by the image sensor, wherein the two I/O address generators of each of the plurality of processing units are configured to control a transfer of the data from the image sensor interface to and from the external memory.

12. The device according to claim 11 , wherein the data cache is disposed between the external memory and the plurality of processing units, and the data cache shares the wafer substrate with the VLIW processor.

13. The device according to claim 12 , wherein the two I/O address generators of each of the plurality of processing units controls the transfer of data from the image sensor interface to and from the data cache.

14. The device according to claim 13 , further comprising a memory interface separate from the image sensor interface and configured to provide an interface between the data cache and the external memory, wherein the memory interface shares the wafer substrate with the VLIW processor.

15. The device according to claim 1 , wherein the interface connecting the plurality of processing units in parallel is a crossbar switch.

16. The device according to claim 1 , wherein the input buffer is separate from the image sensor interface.

17. The device according to claim 16 , wherein the input buffer is configured for receiving data from the image sensor interface and bound for the plurality of processing units.

Assignees

• Silverbrook Kia
• Google Inc

Inventors

• Silverbrook Kia

Classifications

• H10W42/405

  using active circuits · CPC title

• H04N23/843

  Demosaicing, e.g. interpolating colour pixel values · CPC title

• H04N25/00

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• B41J2/14 Primary

  Structure thereof {only for on-demand ink jet heads} · CPC title

• G06F2212/2022

  Flash memory · CPC title