Packet shaping in a network processor

US9559982B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9559982-B2
Application numberUS-201414194038-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2014
Priority dateFeb 28, 2014
Publication dateJan 31, 2017
Grant dateJan 31, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for managing transmittal of packets, the circuit comprising: a packet descriptor manager (PDM) circuit module configured to generate a metapacket from a command signal, the metapacket indicating a size and a destination of a packet to be transmitted by the circuit, the metapacket including an entry stating the size of the packet; a packet scheduling engine (PSE) circuit module configured to compare a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, the PSE determining an order in which to transmit the packet among a plurality of packets based on the comparison; and a packet engines and buffering (PEB) circuit module configured to process the packet and cause a processed packet to be transmitted toward the destination according to the order determined by the PSE; wherein the PSE is further configured to compare, for a plurality of nodes in a path between the circuit and the destination, a packet transmission rate associated with the node against at least one of a peak rate and a committed rate associated with the node, the PSE determining the order based on the comparisons. 2. The circuit of claim 1 , wherein the PSE is further configured to model transmission of the packet through a model of a network topology from the destination to the circuit, the PSE determining the order based on the model transmission. 3. The circuit of claim 2 , wherein the PSE is further configured to model a plurality of nodes having network shapers in the network topology between the destination and the circuit, each of the network shapers defining at least one of a peak rate and a committed rate. 4. The circuit of claim 3 , wherein the PSE is further configured to apply a model of the packet to each of the network shapers in a path between the circuit and the destination, the PSE determining the order based on the application. 5. The circuit of claim 4 , wherein the PSE is further configured to assign a color to each of the network shapers based on a modeled packet rate through the network shaper. 6. The circuit of claim 5 , wherein the PSE is further configured to assign a color to the packet based on the color of at least one of the network shapers in a path of the packet. 7. The circuit of claim 6 , wherein the PSE is further configured to apply rules for assigning the color to the packet based on at least one field of the metapacket. 8. The circuit of claim 2 , wherein the PSE is further configured to determine the order based on arrival of the packet relative to other packets at the circuit in the model transmission. 9. The circuit of claim 7 , wherein the PSE is further configured to model transmission of the plurality of packets from a plurality of respective destinations to the circuit, the PSE determining the order based on arrival of the packet among the plurality of packets in the model transmission. 10. The circuit of claim 8 , wherein the PSE is further configured to model a plurality of nodes in the network topology between the plurality of destinations and the circuit. 11. The circuit of claim 1 , wherein the PSE is further configured to associate the packet transmission rate with the packet based on the destination. 12. The circuit of claim 1 , wherein the PSE is further configured to assign a color to the packet based on the comparison. 13. A method of managing transmittal of packets, the method comprising: receiving a command signal identifying a packet to be processed and transmitted; generating a metapacket from the command signal, the metapacket including an indication of a size of the packet and a destination of the packet, the metapacket including an entry stating the size of the packet; comparing, at a packet scheduling engine (PSE) circuit module, a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet; comparing, for a plurality of nodes in a path between the circuit and the destination, a packet transmission rate associated with the node against at least one of a peak rate and a committed rate associated with the node, determining an order in which to transmit the packet among a plurality of packets based on the comparisons; processing operations on the packet to produce a processed packet; and causing the processed packet to be transmitted toward the destination according to the order. 14. The method of claim 13 , further comprising modeling transmission of the packet through a model of a network topology from the destination to the circuit, the PSE determining the order based on the model transmission. 15. The method of claim 14 , further comprising modeling a plurality of nodes having network shapers in the network topology between the destination and the circuit, each of the network shapers defining at least one of a peak rate and a committed rate. 16. The method of claim 15 , further comprising applying a model of the packet to each of the network shapers in a path between the circuit and the destination, the order being based on the application. 17. The method of claim 16 , further comprising assigning a color to each of the network shapers based on a modeled packet rate through the network shaper. 18. The method of claim 17 , further comprising assigning a color to the packet based on the color of at least one of the network shapers in a path of the packet. 19. The method of claim 18 , further comprising applying rules for assigning the color to the packet based on at least one field of the metapacket. 20. The method of claim 14 , further comprising determining the order based on arrival of the packet relative to other packets at the circuit in the model transmission. 21. The method of claim 20 , further comprising modeling transmission of the plurality of packets from a plurality of respective destinations to the circuit, the order being based on arrival of the packet among the plurality of packets in the model transmission. 22. The method of claim 21 , further comprising modeling a plurality of nodes in the network topology between the plurality of destinations and the circuit.

Assignees

Inventors

Classifications

  • Routing instructions carried by the data packet, e.g. active networks · CPC title

  • Address processing for routing · CPC title

  • Parsing or analysis of headers · CPC title

  • Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

  • H04L49/90Primary

    Buffering arrangements · CPC title

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Frequently asked questions

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What does patent US9559982B2 cover?
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet…
Who is the assignee on this patent?
Cavium Inc
What technology area does this patent fall under?
Primary CPC classification H04L49/90. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).