Semiconductor device

Patent metadata

Field	Value
Publication number	US-9559693-B2
Application number	US-201514866544-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Oct 31, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

First claim

What is claimed is:

1. A semiconductor device including an active mode and a standby mode as operation modes, comprising:
a first power source line which accepts the supply of power in the active mode;
a second power source line which accepts the supply of power in the active mode and the standby mode;
a memory circuit to be coupled with the first and second power source lines; and
a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode,
wherein the memory circuit includes
a memory array to be coupled with the second power source line,
a peripheral circuit to be coupled with the first power source line, and
a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode, and
wherein the first and second switches each includes
a first PMOS transistor a source and an N-type well of which are to be coupled to the first power source line, and
a second PMOS transistor a source and an N-type well of which are to be coupled to the second power source line and a drain of which is to be coupled to a drain of the first PMOS transistor.

2. The semiconductor device according to claim 1 , further comprising:
a first internal power source circuit which supplies a first internal voltage to the first power source line on the basis of an external power source voltage; and
a second internal power source circuit which supplies a second internal voltage to the second power source line on the basis of the external power source voltage.

3. The semiconductor device according to claim 1 , further comprising:
a switch control circuit which controls the first and second switches,
wherein the switch control circuit includes
a first control signal generation unit adapted to generate a first control signal to be input into a gate of each of the first PMOS transistors on the basis of a voltage of the second power source line, and
a second control signal generation unit adapted to generate a second control signal to be input into a gate of each of the second PMOS transistors on the basis of a control command and a voltage of the first power source line.

4. The semiconductor device according to claim 3 ,
wherein the first control signal generation unit generates the first control signal so as to turn the first PMOS transistors on in accordance with the control command to be issued for turning the first PMOS transistors on in a state where the second power source line has risen up to a second internal power source voltage, and
wherein the second control signal generation unit generates the second control signal so as to turn the second PMOS transistors on in accordance with the control command to be issued for turning the second PMOS transistors on in a state where the first power source line has risen up to a first internal power source voltage.

5. A semiconductor device including an active mode and a standby mode as operation modes, comprising:
a first power source line which accepts the supply of power in the active mode;
a second power source line which accepts the supply of power in the active mode and the standby mode;
a plurality of memory circuits to be coupled with the first and second power source lines; and
a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode,
wherein each of the memory circuits includes
a memory array to be coupled with the second power source line,
a peripheral circuit to be coupled with the first power source line, and
a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode, and
wherein the first and second switches each includes
a first PMOS transistor a source and an N-type well of which are to be coupled to the first power source line, and
a second PMOS transistor a source and an N-type well of which are to be coupled to the second power source line and a drain of which is to be coupled to a drain of the first PMOS transistor.

Assignees

• Renesas Electronics Corp

Inventors

• Ishii Yuichiro
• Miyanishi Atsushi
• Yanagisawa Kazumasa

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• H03K19/0016 Primary

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title