Array substrate and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9559690-B2
Application number	US-201414443280-A
Country	US
Kind code	B2
Filing date	Oct 1, 2014
Priority date	May 30, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate comprises: a gate electrode ( 11 ) and a gate line ( 12 ) located on a base substrate ( 00 ); an active layer ( 20 ) located on a film layer where the gate electrode ( 11 ) and the gate line ( 12 ) are located; a drain electrode ( 31 ), a source electrode ( 32 ) and a data line ( 33 ) located on the active layer ( 20 ); a pixel electrode ( 40 ) located on a film layer where the drain electrode ( 31 ), the drain electrode ( 32 ) and the data line ( 33 ) are located and connected to the drain electrode ( 31 ) through a first via hole ( 100 ); and a common electrode layer ( 50 ) located on a film layer where the pixel electrode ( 40 ) is located and insulated from the pixel electrode ( 40 ); wherein, the common electrode layer ( 50 ) includes a plurality of self-capacitive electrodes ( 51 ) disposed on a same layer and mutually insulated; the array substrate further comprises: a plurality of conducting lines ( 60 ), located on the film layer where the drain electrode ( 31 ), the source electrode ( 32 ) and the data line ( 33 ) are located, and insulated from the drain electrode ( 31 ), the source drain ( 32 ), the data line ( 33 ) and the pixel electrode ( 40 ); and, disposed on a layer different from the common electrode layer ( 50 ), and each of the conducting lines ( 60 ) being electrically connected to a corresponding self-capacitive electrode ( 51 ) through a second via hole ( 200 ).

First claim

What is claimed is:

1. An array substrate, comprising: a base substrate; a gate electrode and a gate line located on the base substrate; an active layer located on a film layer where the gate electrode and the gate line are located; a drain electrode, a source electrode and a data line located on the active layer; a pixel electrode located on a film layer where the drain electrode, the source electrode and the data line are located and electrically connected to the drain electrode through a first via hole; and a common electrode layer located on a film layer where the pixel electrode is located and electrically insulated from the pixel electrode; wherein,
the common electrode layer includes a plurality of self-capacitive electrodes disposed on a same layer and mutually insulated;
the array substrate further comprises:
a plurality of conducting lines, located on the film layer where the drain electrode, the source electrode and the data line are located, and electrically insulated from the drain electrode, the source drain, the data line and the pixel electrode; and, disposed on a layer different from the common electrode layer, and each of the conducting lines being electrically connected to a corresponding self-capacitive electrode through a second via hole.

2. The array substrate according to claim 1 , wherein, a film layer where the conducting lines are located is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the common electrode layer.

3. The array substrate according to claim 2 , wherein, the film layer where the conducting lines are located is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the film layer where the pixel electrode is located.

4. The array substrate according to claim 3 , wherein, a first passivation layer is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the film layer where the pixel electrode is located, and the first via hole runs through the first passivation layer;
the film layer where the conducting lines are located is disposed between the first passivation layer and the film layer where the pixel electrode is located;
the array substrate further comprises:
a first insulating layer, located between the film layer where the conducting lines are located and the film layer where the pixel electrode is located, both the first via hole and the second via hole running through the first insulating layer;
wherein, the pixel electrode is electrically connected to the drain electrode through the first via hole.

5. The array substrate according to claim 2 , wherein, the film layer where the conducting lines are located is disposed between the film layer where the pixel electrode is located and the common electrode layer.

6. The array substrate according to claim 5 , wherein, a second passivation layer is disposed between the film layer where the pixel electrode is located and the common electrode layer;
the film layer where the conducting lines are located is disposed between the second passivation layer and the common electrode layer;
the array substrate further comprises:
a second insulating layer, located between the film layer where the conducting lines are located and the common electrode layer, the second via hole running through the second insulating layer.

7. The array substrate according to claim 1 , wherein, the film layer where the conducting lines are located is disposed above the common electrode layer.

8. The array substrate according to claim 7 , further comprising:
a third insulating layer, located between the film layer where the conducting lines are located and the common electrode layer, the second via hole running through the third insulating layer.

9. The array substrate according to claim 1 , wherein, orthogonal projections of the conducting lines on the base substrate are located in an orthogonal projection of the data line on the base substrate; and/or
the orthogonal projections of the conducting lines on the base substrate are located in an orthogonal projection of the gate line on the base substrate.

10. The array substrate according to claim 1 , wherein, the conducting lines serve as common electrode lines for supplying power to the common electrode layer during a display scanning time period.

11. A display device, comprising the array substrate according to claim 1 .

12. The display device according to claim 11 , wherein, a film layer where the conducting lines are located is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the common electrode layer.

13. The display device according to claim 12 , wherein, the film layer where the conducting lines are located is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the film layer where the pixel electrode is located.

14. The display device according to claim 13 , wherein, a first passivation layer is disposed between the film layer where the drain electrode, the source electrode and the data line are located and the film layer where the pixel electrode is located, and the first via hole runs through the first passivation layer;
the film layer where the conducting lines are located is disposed between the first passivation layer and the film layer where the pixel electrode is located;
the array substrate further comprises:
a first insulating layer, located between the film layer where the conducting lines are located and the film layer where the pixel electrode is located, both the first via hole and the second via hole running through the first insulating layer;
wherein, the pixel electrode is electrically connected to the drain electrode through the first via hole.

15. The display device according to claim 12 , wherein, the film layer where the conducting lines are located is disposed between the film layer where the pixel electrode is located and the common electrode layer.

16. The display device according to claim 15 , wherein, a second passivation layer is disposed between the film layer where the pixel electrode is located and the common electrode layer;
the film layer where the conducting lines are located is disposed between the second passivation layer and the common electrode layer;
the array substrate further comprises:
a second insulating layer, located between the film layer where the conducting lines are located and the common electrode layer, the second via hole running through the second insulating layer.

17. The display device according to claim 11 , wherein, the film layer where the conducting lines are located is disposed above the common electrode layer.

18. The display device according to claim 17 , further comprising:
a third insulating layer, located between the film layer where the conducting lines are located and the common electrode layer, the second via hole running through the third insulating layer.

19. The display device according to claim 11 , wherein, orthogonal projections of the conducting lines on the base substrate are located in an orthogonal projection of the data line on the base substrate; and/or
the orthogonal projections of the conducting lines on the base substrate are located in an orthogonal projection of the gate line on the base substrate.

20. A manufacturing method of an array substrate, comprising:
forming a film layer where a gat

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Yang Shengji
• Dong Xue
• Wang Haisheng
• Xue Hailin
• Liu Yingming
• Zhao Weijie
• Liu Hongjuan
• Ding Xiaoliang

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H03K2217/960755

  Constructional details of capacitive touch and proximity switches · CPC title

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• H03K17/962 Primary

  Capacitive touch switches · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title