System and method for a switch having a normally-on transistor and a normally-off transistor

Patent metadata

Field	Value
Publication number	US-9559683-B2
Application number	US-201414473207-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

In accordance with an embodiment, a circuit includes a first driver having a first output configured to be coupled to a control node of a normally-off transistor. The first driver is configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode. The circuit further includes a second driver having a second output configured to be coupled to a control node of a normally-on transistor that has a second load path terminal coupled to a first load path terminal of the normally-off transistor. The second driver is configured to drive a second switching signal at the second output in the direct drive mode.

First claim

What is claimed is:

1. A circuit comprising:
a first driver comprising a first output configured to be coupled to a control node of a normally-off transistor, the first driver configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode, wherein the normally-off transistor has a first load path between a first load path terminal of the normally-off transistor and a second load path terminal of the normally-off transistor; and
a second driver comprising a second output configured to be coupled to a control node of a normally-on transistor, the second driver configured to drive a second switching signal at the second output in the direct drive mode and configured to drive a static signal at the second output in the cascode mode, wherein the normally-on transistor has a second load path between a third load path terminal of the normally-on transistor and a fourth load path terminal of the normally-on transistor, the second load path terminal of the normally-off transistor is coupled to the third load path terminal of the normally-on transistor.

2. The circuit of claim 1 , wherein:
the second driver is further configured to high impedance at the second output in cascode mode; and
the circuit further comprises a switch coupled between the control node of the normally-on transistor and the first load path terminal of the normally-off transistor, the switch configured to be open in the direct drive mode and closed in the cascode mode.

3. The circuit of claim 1 , wherein:
the first driver comprises a first power supply terminal of the first driver and a second power supply terminal of the first driver configured to be coupled to the first load path terminal of the normally-off transistor; and
the second driver comprises a third power supply terminal of the second driver, and a fourth power supply terminal of the second driver configured to be coupled to the third load path terminal of the normally-on transistor.

4. The circuit of claim 3 , wherein:
the first switching signal comprises a voltage that transitions between a voltage of the first power supply terminal of the first driver and a voltage of the first load path terminal of the normally-off transistor; and
the second switching signal comprises a voltage that transitions between a voltage of the third load path terminal of the normally-on transistor and the third power supply terminal of the second driver.

5. The circuit of claim 3 , further comprising:
a first power supply coupled between the first power supply terminal of the first driver and the second power supply terminal of the first driver; and
a second power supply coupled between the third power supply terminal of the second driver and the fourth power supply terminal of the second driver.

6. The circuit of claim 1 , further comprising the normally-on transistor and the normally-off transistor.

7. The circuit of claim 6 , wherein the normally-on transistor comprises a GaN HEMT device and the third load path terminal of the normally-on transistor comprises a source of the GaN HEMT device.

8. The circuit of claim 7 , wherein the normally-off transistor comprises an enhancement mode MOSFET transistor, the second load path terminal of the enhancement mode MOSFET transistor comprises a drain of the enhancement mode MOSFET transistor and the first load path terminal of the enhancement mode MOSFET transistor comprises a source of the enhancement mode MOSFET transistor.

9. A circuit comprising:
a first driver comprising a first output configured to be coupled to a control node of a normally-off transistor, the first driver configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode, wherein the normally-off transistor has a first load path between a first load path terminal of the normally-off transistor and a second load path terminal of the normally-off transistor;
a second driver comprising a second output configured to be coupled to a control node of a normally-on transistor, the second driver configured to drive a second switching signal at the second output in the direct drive mode, wherein the normally-on transistor has a second load path between a third load path terminal of the normally-on transistor and a fourth load path terminal of the normally-on transistor, the second load path terminal of the normally-off transistor is coupled to the third load path terminal of the normally-on transistor, and
a controller configured to
couple an input switching signal to an input of the first driver, assert a control signal that configures the second driver to have a high impedance at the second output, and close the switch in the cascode mode, and
couple the input switching signal to an input of the second driver, apply a constant voltage to an input of the first driver, and open the switch in the direct drive mode.

10. The circuit of claim 9 , wherein the constant voltage comprises a turn-on voltage of the normally-off transistor.

11. A method of operating a switch comprising a normally-on transistor coupled in series with a normally-off transistor, the method comprising: in a cascode mode, driving a first switching signal to a control node of the normally-off transistor using a first driving circuit, and persistently turning on the normally-on transistor having a control node coupled to an output of a second driving circuit, wherein the persistently turning on the normally-on transistor comprises applying a static signal to the control node of the normally-on transistor; and in a direct drive mode, driving a second switching signal to the control node of the normally-on transistor using the second driving circuit, and driving a first constant voltage to the control node of the normally-off transistor using the first driving circuit and opening the switch.

12. The method of claim 11 , further comprising:
in the cascode mode, placing a second driving circuit coupled to the control node of the normally-on transistor in a high output impedance state, and closing a switch coupled between the control node of the normally-on transistor and a load path terminal of the normally-off transistor.

13. The method of claim 12 , wherein the normally-on transistor and the normally-off transistor each comprises a FET transistor and the load path terminal of the normally-off transistor comprises a source of the normally-off transistor.

14. The method of claim 11 , wherein, in the cascode mode, the switch couples the control node of the normally-on transistor to a source terminal of the normally-off transistor.

15. The method of claim 11 , wherein the normally-off transistor comprises an enhancement mode MOSFET and the normally-on transistor comprises a GaN HEMT.

16. The method of claim 11 , further comprising applying a first supply voltage between power supply terminals of the first driving circuit, and applying a second supply voltage between power supply terminals of the second driving circuit.

17. The method of claim 16 , wherein applying the first supply voltage comprises applying a first power supply reference node to a positive supply terminal of the first driving circuit and coupling a load terminal of the normally-off transistor to a negative supply terminal of the first driving circuit.

18. The method of claim 16 , wherein applying the second supply voltage comprises applying a second power supply reference node to a negative suppl

Assignees

• Infineon Technologies Austria Ag

Inventors

• Zojer Bernhard

Classifications

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K17/107 Primary

  in composite switches · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H02M7/1626

  with automatic control of the output voltage or current · CPC title