Protected switching element

US9559682B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9559682-B2
Application numberUS-201514594957-A
CountryUS
Kind codeB2
Filing dateJan 12, 2015
Priority dateJan 12, 2015
Publication dateJan 31, 2017
Grant dateJan 31, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A circuit is suggested comprising an electronic switching element, a logic unit coupled to control the electronic switching element, and a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply.

First claim

Opening claim text (preview).

The invention claimed is: 1. A circuit comprising an electronic switching element, a logic unit coupled to control the electronic switching element, and a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply, wherein the internal power supply is arranged to provide power to the counter unit in case an external supply voltage for the circuit gets interrupted. 2. The circuit according to claim 1 , wherein the electronic switching element comprises at least one transistor with a current sense unit, wherein the current sense unit is connected to the logic unit. 3. The circuit according to claim 1 , wherein the counter unit comprises a supply decoupling unit that is coupled to the internal power supply, wherein the supply decoupling unit is arranged to determine an interruption in the external supply voltage and based on such interruption to decouple the external supply voltage from the counter unit such that the counter unit is buffered by the internal power supply. 4. The circuit according to claim 3 , wherein the supply decoupling unit and the internal power supply are coupled to a supply supervision unit, wherein the supply supervision unit is arranged to issue a signal to reset the counter. 5. The circuit according to claim 4 , wherein the supply supervision unit is arranged to issue the signal to reset the counter in case the power provided by the internal power supply reaches and/or falls below a predetermined threshold. 6. The circuit according to claim 4 , wherein the supply supervision unit is arranged to stop issuing the signal to reset the counter in case the external supply voltage has been switched on. 7. The circuit according to claim 4 , wherein the supply supervision unit is arranged to stop issuing the signal to reset the counter a predetermined time after an enablement of the external supply voltage has been detected. 8. The circuit according to claim 1 , wherein the counter unit comprises an input for resetting the counter. 9. The circuit according to claim 1 , wherein the counter of the counter unit is arranged for counting events, wherein signals corresponding to events are supplied by the logic unit. 10. The circuit according to claim 9 , wherein the event may be at least one of the following: an over-temperature condition, a temperature difference excess, an over-current condition, an overload condition, a fault condition, any preferred signal or event. 11. The circuit according to claim 9 , wherein the counter unit comprises a first comparing unit determining whether the counted events reach a predetermined threshold. 12. The circuit according to claim 9 , wherein the counter unit comprises a second comparing unit determining whether the counted events is zero or different from zero. 13. The circuit according to claim 1 , wherein the counter unit comprises a storage element for storing at least one information, wherein the internal power supply is arranged to provide power for buffering the at least one information in case an external supply voltage for the circuit gets interrupted. 14. The circuit according to claim 1 , wherein the internal power supply comprises at least one capacitor that is charged via an external supply voltage. 15. The circuit according to claim 1 , wherein the electronic switching element is implemented as a high-side switch or as a low-side switch. 16. A device comprising at least one circuit that includes: an electronic switching element, a logic unit coupled to control the electronic switching element, a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply, wherein the internal power supply is arranged to provide power to the counter unit in case an external supply voltage for the circuit gets interrupted. 17. The device according to claim 16 , wherein the device is a protected field effect transistor. 18. A method for operating a circuit that comprises: an electronic switching element, a logic unit coupled to control the electronic switching element, a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply, wherein the internal power supply is arranged to provide power to the counter unit in case an external supply voltage for the circuit gets interrupted, the method comprising: determining an interruption in the external supply voltage, based on such interruption, decoupling the external supply voltage from the counter unit such that the counter unit is buffered by the internal power supply. 19. The method according to claim 18 comprising: counting events by the counter of the counter unit, wherein signals corresponding to events are supplied by the logic unit. 20. The method according to claim 18 comprising: issuing a signal to reset the counter in case the power provided by the internal power supply reaches and/or falls below a predetermined threshold. 21. The method according to claim 18 comprising: stop issuing the signal to reset the counter a predetermined time after an enablement of the external supply voltage has been detected. 22. A device comprising: means for determining an interruption in an external supply voltage, based on such interruption, means for decoupling the external supply voltage from a counter unit such that the counter unit is buffered by an internal power supply.

Assignees

Inventors

Classifications

  • Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection (specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems H02H7/00; systems for change-over to standby supply H02J9/00 ){; integrated protection (for motors H02H7/0822)} · CPC title

  • Modifications for resetting core switching units to a predetermined state · CPC title

  • in field-effect transistor switches · CPC title

  • Storing the actual state when the supply voltage fails · CPC title

  • H03K17/08Primary

    Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9559682B2 cover?
A circuit is suggested comprising an electronic switching element, a logic unit coupled to control the electronic switching element, and a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H03K17/0822. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).