Method of fabricating a three-dimensional (3D) porous electrode architecture for a microbattery

Patent metadata

Field	Value
Publication number	US-9559349-B2
Application number	US-201414321077-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 29, 2011
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A method of fabricating a 3D porous electrode architecture comprises forming a microbattery template that includes (a) a lattice structure comprising a first lattice portion separated from a second lattice portion on a substrate, and (b) a solid structure on the substrate including a separating portion between the first and second lattice portions. Interstices of the first lattice portion are infiltrated with a first conductive material and interstices of the second lattice portion are infiltrated with a second conductive material. Each of the first and second conductive materials fill the interstices to reach a predetermined thickness on the substrate. The solid structure and the lattice structure are removed from the structure, thereby forming first and second conductive scaffolds comprising a porosity defined by the lattice structure and having a lateral size and shape defined by walls of the solid structure.

First claim

The invention claimed is:

1. A method of fabricating a three-dimensional (3D) porous electrode architecture for a microbattery, the method comprising:
forming a microbattery template comprising:
a lattice structure comprising a first lattice portion separated from a second lattice portion on a substrate; and
a solid structure on the substrate at least partly surrounding the first and second lattice portions, the solid structure comprising a separating portion disposed between the first and second lattice portions;

infiltrating interstices of the first lattice portion with a first conductive material and infiltrating interstices of the second lattice portion with a second conductive material, each of the first and second conductive materials filling the interstices to reach a predetermined thickness on the substrate;
removing the solid structure and the lattice structure from the substrate, thereby forming first and second conductive scaffolds from the first and second conductive materials, the first and second conductive scaffolds comprising a porosity defined by the lattice structure and having a lateral size and shape defined by walls of the solid structure.

2. The method of claim 1 , further comprising:
conformally depositing an anode active material on the second conductive scaffold to form a porous anode; and
conformally depositing a cathode active material on the first conductive scaffold to form a porous cathode.

3. The method of claim 1 , wherein the solid structure surrounds the first and second lattice portions on all sides.

4. The method of claim 1 , wherein one or more of the walls of the solid structure are normal to the substrate.

5. The method of claim 1 , wherein the lattice structure is formed before the solid structure is formed.

6. The method of claim 1 , wherein the lattice structure is formed after the solid structure is formed.

7. The method of claim 1 , wherein forming the microbattery template comprises:
applying a photoresist to the substrate;
patterning the photoresist using a 2D pattern to form the solid structure;
patterning the photoresist using a 3D pattern to form the lattice structure.

8. The method of claim 7 ,
wherein patterning the photoresist using the 2D pattern comprises:
exposing the photoresist to light passing through a 2D mask pattern to create in the photoresist at least one mask-defined exposed region and at least one mask-defined unexposed region, and
developing the photoresist to selectively remove the at least one mask-defined exposed region or the at least one mask-defined unexposed region from the substrate, thereby forming the solid structure, and

wherein patterning the photoresist using the 3D pattern comprises:
exposing the photoresist to a 3D interference pattern of light comprising areas of constructive interference and destructive interference to create in the photoresist a plurality of interference-defined exposed regions and a plurality of interference-defined unexposed regions, and
developing the photoresist to selectively remove the plurality of interference-defined exposed regions or the plurality of interference-defined unexposed regions, thereby forming the lattice structure.

9. The method of claim 8 , wherein the photoresist comprises a negative photoresist, and wherein the photoresist is developed only after the exposure of the photoresist to the 2D mask pattern and to the 3D interference pattern, thereby selectively removing the plurality of interference-defined unexposed regions and the at least one mask-defined unexposed region substantially simultaneously.

10. The method of claim 7 , further comprising reapplying the photoresist to the substrate after patterning the photoresist with the 2D pattern or with the 3D pattern, such that one of the solid structure and the lattice structure is formed after the reapplying of the photoresist.

11. The method of claim 1 , wherein forming the microbattery template comprises:
applying a first photoresist to the substrate;
patterning the first photoresist using a 2D pattern to form the solid structure;
applying a second photoresist of opposite tone to the first photoresist to the substrate;
patterning the second photoresist using a 3D pattern to form the lattice structure.

12. The method of claim 11 , wherein patterning the first photoresist comprises:
exposing the first photoresist to light passing through a 2D mask pattern to create in the first photoresist at least one mask-defined exposed region and at least one mask-defined unexposed region, and
developing the first photoresist to selectively remove the at least one mask-defined exposed region or the at least one mask-defined unexposed region from the substrate, thereby forming the solid structure, and
wherein patterning the second photoresist comprises:
exposing the second photoresist to a 3D interference pattern of light comprising areas of constructive interference and destructive interference to create in the second photoresist a plurality of interference-defined exposed regions and a plurality of interference-defined unexposed regions, and
developing the second photoresist to selectively remove the plurality of interference-defined exposed regions or the plurality of interference-defined unexposed regions, thereby forming the lattice structure.

13. The method of claim 12 , wherein the first photoresist comprises a negative photoresist and the at least one mask-defined unexposed region is selectively removed from the substrate, and
wherein the second photoresist comprises a positive photoresist and the plurality of interference-defined exposed regions are selectively removed from the substrate.

14. The method of claim 12 , wherein the first photoresist comprises a positive photoresist and the at least one mask-defined exposed region is selectively removed from the substrate, and
wherein the second photoresist comprises a negative photoresist and the plurality of interference-defined unexposed regions are selectively removed from the substrate.

15. The method of claim 1 , wherein forming the microbattery template comprises:
depositing a colloidal solution comprising a plurality of microparticles onto the surface, the microparticles assembling into the lattice structure;
applying a photoresist to the substrate;
patterning the photoresist using a 2D pattern to form the solid structure.

16. The method of claim 15 , wherein patterning the photoresist using the 2D pattern comprises:
exposing the photoresist to light passing through a 2D mask pattern to create in the photoresist at least one mask-defined exposed region and at least one mask-defined unexposed region, and
after the exposure, developing the photoresist to selectively remove the at least one mask-defined exposed region or the at least one mask-defined unexposed region from the substrate, thereby forming the solid structure.

17. The method of claim 1 , wherein each of the first conductive material and the second conductive material comprises at least one element selected from the group consisting of: C, Co, Cr, Cu, Ag, Au, W, Mn, Mo, Zn, Ni, Pt, Re, Sn, Ti, Ta, Al, Si, N, and Fe.

18. The method of claim 1 , wherein an electrically conductive coating is deposited on the substrate prior to forming the lattice structure and the solid structure, and further comprising patterning the electrically conductive coating, thereby forming first and second conductive patterns on the substrate.

19. The method of claim 18 , wherein the first and second conductive patterns are formed afte

Assignees

• Univ Illinois

Inventors

• Braun Paul V
• Ning Hailong
• Arpin Kevin A

Classifications

• B33Y80/00

  Products made by additive manufacturing · CPC title

• H01M4/80

  Porous plates, e.g. sintered carriers · CPC title

• H01M4/0404

  by coating on electrode collectors · CPC title

• H01M4/04 Primary

  Processes of manufacture in general · CPC title

• G03F7/0035

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title