Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9559212-B2
Application number	US-201514810700-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Nov 13, 2008
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor. In a thin film transistor including an oxide semiconductor layer, a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor is formed over the oxide semiconductor layer, whereby field effect mobility of the thin film transistor can be increased. Further, by forming a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor between the oxide semiconductor layer and a protective insulating layer of the thin film transistor, change in composition or deterioration in film quality of the oxide semiconductor layer is prevented, so that electrical characteristics of the thin film transistor can be stabilized.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first non-single crystalline oxide semiconductor layer comprising indium on an insulating surface, the first non-single crystalline oxide semiconductor layer having a first conductivity;
a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity higher than the first conductivity;
a gate electrode, wherein the gate electrode is overlapped with the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer; and
an insulating film on the second non-single crystalline oxide semiconductor layer,
wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10 19 /cm 3 or lower.

2. The semiconductor device according to claim 1 , wherein the insulating film comprises silicon and oxygen.

3. The semiconductor device according to claim 1 , further comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode are in contact with the first non-single crystalline oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

5. The semiconductor device according to claim 1 , wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.

6. The semiconductor device according to claim 1 , further comprising a gate insulating film comprising silicon and oxygen adjacent to the gate electrode.

7. The semiconductor device according to claim 1 , wherein the gate electrode is located below the first non-single crystalline oxide semiconductor layer.

8. The semiconductor device according to claim 1 , wherein the semiconductor device is one selected from the group consisting of an electronic paper, an electronic book reader, a television set, a digital photo frame, a portable game machine, a slot machine, and a mobile phone.

9. A semiconductor device comprising:
a first non-single crystalline oxide semiconductor layer comprising indium on an insulating surface, the first non-single crystalline oxide semiconductor layer having a first conductivity;
a second non-single crystalline oxide semiconductor layer comprising indium over the first non-single crystalline oxide semiconductor layer, the second non-single crystalline oxide semiconductor layer having a second conductivity higher than the first conductivity;
a gate electrode, wherein the gate electrode is overlapped with the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer;
an insulating film on the second non-single crystalline oxide semiconductor layer;
a source electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a first buffer region having n-type conductivity; and
a drain electrode in electrical contact with the first non-single crystalline oxide semiconductor layer through a second buffer region having n-type conductivity,
wherein each of the first buffer region and the second buffer region comprises crystal grains of an oxide semiconductor material comprising indium, and
wherein a concentration of sodium in the first non-single crystalline oxide semiconductor layer is 5×10 19 /cm 3 or lower.

10. The semiconductor device according to claim 9 , wherein the insulating film comprises silicon and oxygen.

11. The semiconductor device according to claim 9 , wherein each of the first non-single crystalline oxide semiconductor layer and the second non-single crystalline oxide semiconductor layer further comprises gallium and zinc.

12. The semiconductor device according to claim 9 , wherein a thickness of the first non-single crystalline oxide semiconductor layer is 10 nm to 300 nm.

13. The semiconductor device according to claim 9 , further comprising a gate insulating film comprising silicon and oxygen adjacent to the gate electrode.

14. The semiconductor device according to claim 9 , wherein the gate electrode is located below the first non-single crystalline oxide semiconductor layer.

15. The semiconductor device according to claim 9 , wherein the oxide semiconductor material of the crystal grains further comprises gallium and zinc.

16. The semiconductor device according to claim 9 , further comprising a pixel electrode in electrical contact with one of the source electrode and the drain electrode.

17. The semiconductor device according to claim 9 , wherein a carrier concentration of the first buffer region and the second buffer region is 1×10 18 /cm 3 or higher.

18. The semiconductor device according to claim 9 , wherein the semiconductor device is one selected from the group consisting of an electronic paper, an electronic book reader, a television set, a digital photo frame, a portable game machine, a slot machine, and a mobile phone.

Assignees

• Semiconductor Energy Lab

Inventors

• Kuwabara Hideaki
• Akimoto Kengo
• Sasaki Toshinari

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H01L29/24

  Electricity · mapped topic