Semiconductor film, transistor, semiconductor device, display device, and electronic appliance

Patent metadata

Field	Value
Publication number	US-9559174-B2
Application number	US-201615068708-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Feb 21, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer comprising In, Ga, and Zn; and
an insulating layer that contains oxygen in excess of the stoichiometric composition,
wherein the insulating layer and the oxide semiconductor layer overlap each other,
wherein an atomic ratio of In to Ga and Zn in the oxide semiconductor layer satisfies In:Ga:Zn=x:y:z,
wherein, in an equilibrium diagram with vertices of the three elements of In, Ga, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order, and
wherein the oxide semiconductor layer includes a plurality of crystals.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a nanocrystal.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

4. A transistor comprising the semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a channel region.

5. The semiconductor device according to claim 1 , further comprising:
a second oxide layer; and
a third oxide layer,
wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and
wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

6. The semiconductor device according to claim 5 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

7. The semiconductor device according to claim 5 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

8. A semiconductor device comprising:
an oxide semiconductor layer comprising In, an element M, and Zn, and
an insulating layer that contains oxygen in excess of the stoichiometric composition,
wherein the insulating layer and the oxide semiconductor layer overlap each other,
wherein the element M is at least one of aluminum, gallium, yttrium, and tin,
wherein an atomic ratio of In to the element M and Zn in the oxide semiconductor layer satisfies In:M:Zn=x:y:z,
wherein, in an equilibrium diagram with vertices of the three elements of In, the element M, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order, and
wherein the oxide semiconductor layer includes a plurality of crystals.

9. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes a nanocrystal.

10. The semiconductor device according to claim 9 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

11. A transistor comprising the semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes a channel region.

12. The semiconductor device according to claim 8 , further comprising:
a second oxide layer; and
a third oxide layer,
wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and
wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

13. The semiconductor device according to claim 12 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

14. The semiconductor device according to claim 12 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

15. An semiconductor device comprising:
an oxide semiconductor layer comprising In, Ga, and Zn; and
an insulating layer that contains oxygen in excess of the stoichiometric composition,
wherein the insulating layer and the oxide semiconductor layer overlap each other,
wherein an atomic ratio of In to Ga and Zn in the oxide semiconductor layer satisfies In:Ga:Zn=x:y:z,
wherein, in an equilibrium diagram with vertices of the three elements of In, Ga, and Zn, the atomic ratio is within a range of an area surrounded by line segments that connect first coordinates (x:y:z=35:20:22), second coordinates (x:y:z=7:4:11), third coordinates (x:y:z=5:1:6), fourth coordinates (x:y:z=25:10:14), and the first coordinates, in this order,
wherein the oxide semiconductor layer includes a plurality of crystals, and
wherein In:Ga=2:1.

16. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a nanocrystal.

17. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a plurality of c-axis aligned crystals.

18. A transistor comprising the semiconductor device according to claim 15 , wherein the oxide semiconductor layer includes a channel region.

19. The semiconductor device according to claim 15 , further comprising:
a second oxide layer; and
a third oxide layer,
wherein the oxide semiconductor layer is in contact with a top surface of the second oxide layer, and
wherein the third oxide layer is in contact with a top surface of the oxide semiconductor layer.

20. The semiconductor device according to claim 19 , wherein the third oxide layer is in contact with a side surface of the second oxide layer, and a side surface and the top surface of the oxide semiconductor layer.

21. The semiconductor device according to claim 19 , wherein electron affinity of oxide included in the oxide semiconductor layer is larger than electron affinity of oxide included in the second oxide layer and electron affinity of oxide included in the third oxide layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Shimomura Akihisa
• Yamane Yasumasa
• Sato Yuhei
• Ishiyama Takahisa
• Okazaki Kenichi
• Kawanabe Chiho
• Oota Masashi
• Ishihara Noritaka

Classifications

• C01P2002/89

  by mass-spectroscopy · CPC title

• C01P2004/04

  obtained by TEM, STEM, STM or AFM · CPC title

• C01P2002/72

  by d-values or two theta-values, e.g. as X-ray diagram · CPC title

• C01G15/006 Primary

  Compounds containing gallium, indium or thallium, with or without oxygen or hydrogen, and containing two or more other elements · CPC title

• C01P2006/40

  Electric properties · CPC title