Thin film transistor array panel

Patent metadata

Field	Value
Publication number	US-9559127-B2
Application number	US-201414585336-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 31, 2013
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (ε) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms.

First claim

What is claimed is:

1. A thin film transistor array panel comprising:
an insulation substrate comprising a pixel area;
a gate line and a first electrode on the insulation substrate;
a second electrode which forms an electric field with the first electrode;
a gate insulating layer between the second electrode and the first electrode which form the electric field;
a data line on the gate insulating layer; and
a passivation layer on the gate insulating layer and the data line, and between the gate insulating layer and the second electrode which forms the electric field with the first electrode,
wherein
the first electrode has a planar shape covering the entire pixel area,
the second electrode comprises a plurality of branch electrodes spaced apart from each other, and
a ratio W/S of a width W of the branch electrodes to an interval S between adjacent branch electrodes, and a total thickness T defined by a sum of thicknesses of the gate insulating layer and the passivation layer between the first electrode and the second electrode which form the electric field, satisfy Equation 1:
0.16 T+ 0.38 <W/S <− 0.16 T + 0.48   Equation 1.

2. The thin film transistor array panel of claim 1 , wherein
relative permittivity (ε) of the gate insulating is more than about 15, and
a thickness of the gate insulating layer is less than about 2000 angstroms.

3. The thin film transistor array panel of claim 2 , wherein
relative permittivity (ε) of the passivation layer is more than about 4.0, and a thickness of the passivation layer is less than about 2000 angstroms.

4. The thin film transistor array panel of claim 3 , wherein
the gate insulating layer comprises hafnium oxide or tantalum oxide.

5. The thin film transistor array panel of claim 4 , wherein the passivation layer comprises:
an organic material comprising a polyimide or polymethylmethacrylate, or
an inorganic material comprising silicon oxide.

6. The thin film transistor array panel of claim 2 , wherein the thickness of the gate insulating layer is less than about 1800 angstroms.

7. The thin film transistor array panel of claim 1 , wherein relative permittivity (ε) of the passivation layer is more than about 4.0, and a thickness of the passivation layer is less than about 2000 angstroms.

8. The thin film transistor array panel of claim 7 , wherein the gate insulating layer comprises hafnium oxide or tantalum oxide.

9. The thin film transistor array panel of claim 8 , wherein the passivation layer comprises:
an organic material comprising a polyimide or polymethylmethacrylate, or
an inorganic material comprising silicon oxide.

10. The thin film transistor array panel of claim 1 , wherein
the gate insulating layer comprises hafnium oxide or tantalum oxide.

11. The thin film transistor array panel of claim 10 , wherein the passivation layer comprises:
an organic material comprising a polyimide or polymethylmethacrylate, or
an inorganic material comprising silicon oxide.

12. The thin film transistor array panel of claim 1 , wherein the gate line and the first electrode which forms the electric field with the second electrode, are in a same layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Inoue Daisuke
• Kim Mi Suk
• Kim Si Heun
• Kim Tae Ho
• Park So Youn
• Oh Keun Chan
• Lee Chang-Hun

Classifications

• G02F1/1365

  in which the switching element is a two-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F1/133345 Primary

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• H01L29/517

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic