Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9559058-B2
Application number	US-201213434360-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Nov 14, 2007
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate, including an element region in which one or more transistor elements, each having a gate electrode and a diffusion region of p-type or n-type, are formed;
an insulating film containing oxygen disposed over the element region of the semiconductor substrate;
an interconnection groove formed in the insulating film;
a diffusion preventing film containing manganese for preventing a diffusion of copper conformally formed over an inner wall of the interconnection groove;
a first film containing copper and manganese conformally formed on the inner wall of the diffusion preventing film;
a second film containing copper conformally formed on the first film and filled in the interconnection groove;
an oxide layer containing manganese conformally formed between the first film and the second film,
wherein a manganese concentration of the diffusion preventing film is higher than manganese concentration of the first film, and
wherein the interconnection groove including the diffusion preventing film, the first film, the second film and the oxide layer constitutes an interconnection pattern for connecting the diffusion region of the transistor elements.

2. The semiconductor device according to claim 1 , wherein the diffusion preventing film comprises at least one element selected from the group consisting of Ta, Ti, Zr, and Ru.

3. The semiconductor device according to claim 1 , wherein the film thickness of the first film is within the range of 1 nm to 15 nm.

4. The semiconductor device according to claim 1 , further comprising a cap layer formed over the interconnection groove.

5. The semiconductor device according to claim 4 , the cap layer comprises at least one element selected from the group consisting of SiN and SiC.

6. The semiconductor device according to claim 1 , wherein the second film is formed on the first film by electroplating using the first film as a seed layer.

7. The semiconductor device according to claim 1 , wherein the oxide layer is formed at a distance equal to a thickness of the first film from the diffusion preventing film.

8. The semiconductor device according to claim 1 , wherein the manganese concentration of the first film has a varied distribution in which the manganese concentration is higher nearer to the diffusion preventing film.

Assignees

• Haneda Masaki
• Sunayama Michie
• Shimizu Noriyoshi
• Ohtsuka Nobuyuki
• Nakao Yoshiyuki
• Tabira Takahiro
• Fujitsu Semiconductor Ltd

Inventors

• Haneda Masaki
• Sunayama Michie
• Shimizu Noriyoshi
• Ohtsuka Nobuyuki
• Nakao Yoshiyuki
• Tabira Takahiro

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/043

  for electroplating · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title