Method of forming shallow trench isolations for a semiconductor device

Patent metadata

Field	Value
Publication number	US-9559017-B2
Application number	US-201514819508-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Aug 28, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a first region and a second region;
forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate;
forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench;
performing a rapid thermal oxy-nitridation process on the first liner layer releasing a tensile stress between the first liner layer and the substrate;
removing a portion of the first liner layer in the first region exposing the first trench;
forming a second liner layer on the side and bottom surfaces of the first trench, the second liner layer being made of a material different than that of the first liner layer, and tensile stress between the second liner layer and the substrate being more than that between the first liner layer and the substrate;
forming an isolation film on the first liner layer and the second liner layer; and
performing a planarization process on the isolation film until the substrate is exposed, thus forming shallow trench isolation structures in the first trench and the second trench.

2. The method according to claim 1 , wherein:
the first liner layer is made of silicon oxide before the rapid thermal oxy-nitridation process; and
the first liner layer is transformed to silicon oxynitride after the rapid thermal oxy-nitridation process.

3. The method according to claim 1 , wherein:
the first liner layer is formed by an in situ steam generation (ISSG) process.

4. The method according to claim 1 , wherein:
the second liner layer is made of silicon oxide.

5. The method according to claim 1 , wherein:
the rapid thermal oxy-nitridation process includes a rapid thermal nitridation process and a rapid thermal oxidation process.

6. The method according to claim 5 , wherein:
a source gas of the rapid thermal nitridation process is a nitrogen-contained gas;
a flow rate of the nitrogen-contained gas is in a range of 8 slm-12 slm;
a pressure of the rapid thermal nitridation process is in a range of 600 Torr-700 Torr; and
a temperature of the rapid thermal nitridation process is in a range of 750° C.-850° C.

7. The method according to claim 5 , wherein:
a source gas of the rapid thermal oxidation process includes one or more of N 2 O, O 2 , and H 2 O; and
a temperature of the rapid thermal oxidation process is in a range of 1000° C.-1200° C.

8. The method according to claim 1 , wherein:
the portion of the first liner layer in the first region is removed by a wet etching process.

9. The method according to claim 8 , wherein:
an etching solution of the wet etching process includes HF, H 2 SO 4 , H 2 O 2 and H 2 O.

10. The method according to claim 1 , wherein forming a first trench and a second trench further includes:
forming a mask layer exposing portions of the surface of the substrate in the first region and the second region; and
etching the substrate using the mask layer as an etching mask.

11. The method according to claim 10 , after forming the first trench and the second trench, further including:
performing a pull back process to expose a portion of the surface of the substrate around the first trench and the second trench.

12. The method according to claim 10 , wherein:
the mask layer is a single layer structure made of silicon nitride.

13. The method according to claim 10 , wherein:
the mask layer include a silicon oxide layer formed on the surface of the substrate; and a silicon nitride layer formed on the silicon oxide layer.

14. The method according to claim 1 , wherein:
NMOS transistors are formed in the first region of the substrate; and
PMOS transistors are formed in the second region of the substrate.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xu Kuan
• Chen Wujia

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title