Method and apparatus for controlling current in an array cell

Patent metadata

Field	Value
Publication number	US-9558797-B2
Application number	US-201615095482-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	Apr 14, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

First claim

What is claimed is:

1. A method for controlling current in an array cell, comprising:
applying a supply voltage to a first access point of a transistor that is operatively coupled to the array cell;
precharging a second access point of the transistor to a predetermined voltage;
applying a control voltage to a third access point of the transistor; and
discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

2. The method of claim 1 , wherein a current control device precharges the second access point of the transistor by connecting the second access point of the transistor to a predetermined voltage and discharges the second access point of the transistor by connecting the second access point of the transistor to a further supply voltage.

3. The method of claim 1 , wherein precharging the second access point of the transistor is carried out by using a first current control device which connects the second access point of the transistor to the supply voltage, controls a current such that the second access point of the transistor is charged to a predetermined voltage, and disconnects the second access point of the transistor from the supply voltage before the second access point of the transistor is discharged by means of a second current control device.

4. The method of claim 1 , wherein the second access point of the transistor is discharged with a constant current.

5. The method of claim 1 , wherein the supply voltage is a supply voltage of a bit line connected to the array cell.

6. The method of claim 1 , wherein the control voltage is a select voltage of a word line connected to the array cell.

7. The method of claim 1 , wherein the acts of connecting a first access point of a transistor to a supply voltage, precharging the second access point of the transistor, and applying the control voltage to the third access point of the transistor are carried out substantially simultaneously.

8. An apparatus for controlling current in an array cell, the apparatus comprising:
a transistor that is operatively coupled to the array cell having a first access point, a second access point and a third access point and configured to receive a supply voltage via the first access point and a control voltage via the third access point;
a first current control device configured to precharge the second access point of the transistor to a predetermined voltage; and
a second current control device configured to discharge the second access point of the transistor upon receiving the control voltage via the third access point, thus turning on the transistor which causes a current flow through the array cell connected to the transistor.

9. The apparatus of claim 8 , wherein the first current control device is configured to precharge the second access point of the transistor to a predetermined voltage by connecting the second access point of the transistor to the supply voltage, controlling a current such that the second access point of the transistor is charged to a predetermined voltage and disconnecting the second access point of the transistor from the supply voltage before the second access point of the transistor is discharged by the second current control device.

10. The apparatus of claim 8 , wherein the second current control device is configured to discharge the second access point of the transistor with a constant current.

11. The apparatus of claim 8 , wherein the transistor is an n-channel field effect transistor.

12. The apparatus of claim 11 , wherein the predetermined voltage is equal to or smaller than the supply voltage and greater than a voltage obtained by subtracting a threshold voltage of the n-channel field effect transistor from the control voltage applied to the third access point of the transistor.

13. The apparatus of claim 8 , wherein the supply voltage is a supply voltage of a bit line connected to the array cell.

14. The apparatus of claim 8 , wherein the control voltage is a select voltage of a word line connected to the array cell.

15. The apparatus of claim 8 , wherein the array cell is a memory array cell.

16. An apparatus for controlling current in an array cell, the apparatus comprising:
means for applying a supply voltage to a first access point of a transistor that is operatively coupled to the array cell;
means for precharging a second access point of the transistor;
means for applying a control voltage to a third access point of the transistor; and
means for discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.

17. The apparatus of claim 16 , wherein the means for precharging and the means for discharging are comprised in a current control device which is configured to precharge the second access point of the transistor by connecting the second access point of the transistor to a predetermined voltage and to discharge the second access point of the transistor by connecting the second access point of the transistor to a further supply voltage.

18. The apparatus of claim 16 , wherein the means for precharging the second access point of the transistor are configured to connect the second access point of the transistor to the supply voltage, control a current such that the second access point of the transistor is charged to a predetermined voltage, and disconnect the second access point of the transistor from the supply voltage before the second access point of the transistor is discharged by the means for discharging the second access point of the transistor.

Assignees

• Infineon Technologies Ag

Inventors

• Curatolo Giacomo
• Allers Wolf

Classifications

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title