Flat panel display device controlling initialization of data lines supplied to a pixel unit

Patent metadata

Field	Value
Publication number	US-9558705-B2
Application number	US-201313939017-A
Country	US
Kind code	B2
Filing date	Jul 10, 2013
Priority date	Jan 10, 2013
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A flat panel display device includes a pixel unit having scan-lines, data-lines, and first through third pixels that are coupled to the scan-lines and the data-lines, a scan driver that applies a scan signal to the pixel unit, a data driver that selectively applies a first data signal, a second data signal, a third data signal, and an initialization signal to the pixel unit, a demultiplexing unit having at least one demultiplexer that applies the first data signal, the second data signal, and the third data signal to the first pixels, the second pixels, and the third pixels, respectively, and that simultaneously applies the initialization signal to the first through third pixels, and a timing control unit that controls the scan driver, the data driver, and the demultiplexing unit.

First claim

What is claimed is:

1. A flat panel display device comprising:
a pixel unit having scan-lines, data-lines, and first through third pixels that are coupled to the scan-lines and the data-lines;
a scan driver configured to apply a scan signal to the pixel unit;
a data driver configured
to selectively apply a first data signal, a second data signal, a third data signal, and an initialization signal to the pixel unit,
to directly apply one of the first data signal, the second data signal, and the third data signal to the pixel unit and;

a demultiplexing unit configured
to apply the remaining two of the first data signal, the second data signal, and the third data signal to two of the first pixels, the second pixels, and the third pixels, respectively, and
to simultaneously apply the initialization signal to the two of the first through third pixels, the demultiplexing unit having at least one demultiplexer; and

a timing control unit configured to control the scan driver, the data driver, and the demultiplexing unit, the timing control unit applying a plurality of switching signals to the demultiplexing unit, the initialization signal being applied to the two of the first through third pixels when each of the plurality of switching signals have a same low logic level as a scan signal.

2. The device of claim 1 , further comprising:
a plurality of capacitors configured to store respective voltages corresponding to the first data signal, the second data signal, the third data signal, and the initialization signal, the capacitors being coupled to the data-lines, respectively.

3. The device of claim 1 , wherein a voltage level of the initialization signal is smaller than or equal to respective voltage levels of the remaining two of the first data signal, the second data signal, and the third data signal.

4. The device of claim 1 , wherein the demultiplexer includes:
a plurality of switches configured to perform a coupling operation between the data driver and the data-lines based on a control signal output from the timing control unit; and
a plurality of control-lines configured to apply the control signal to the switches.

5. The device of claim 1 , wherein the timing control unit controls the data driver and the demultiplexing unit
to simultaneously apply the initialization signal to the remaining two of the first through third pixels to initialize the data-lines coupled to the two of the first through third pixels, and
to sequentially apply the two of the first data signal, the second data signal, and the third data signal to the two of the first pixels, the second pixels, and the third pixels, respectively, during one horizontal period.

6. The device of claim 5 , wherein the timing control unit controls the scan driver to apply the scan signal to the two of the first through third pixels after the data-lines coupled to the two of the first through third pixels are initialized, during the one horizontal period.

7. A flat panel display device comprising:
a pixel unit having scan-lines, data-lines, and first through third pixels that are coupled to the scan-lines and the data-lines;
a scan driver configured to apply a scan signal to the pixel unit;
a data driver configured
to selectively apply a first data signal, a second data signal, a third data signal, and an initialization signal to the pixel unit, and
to directly apply one of the first data signal, the second data signal, and the third data signal to the pixel unit;

a demultiplexing unit configured
to apply the remaining two of the first data signal, the second data signal, and the third data signal to two of the first pixels, the second pixels, and the third pixels, respectively, and
to selectively apply the initialization signal to the two of the first through third pixels, the demultiplexing unit having at least one demultiplexer; and

a timing control unit configured to control the scan driver, the data driver, and the demultiplexing unit.

8. The device of claim 7 , wherein the demultiplexer includes:
a plurality of switches configured to perform a coupling operation between the data driver and the data-lines based on a control signal output from the timing control unit; and
a plurality of control-lines configured to apply the control signal to the switches.

9. The device of claim 7 , the timing control unit controlling, during one horizontal period, the data driver and the demultiplexing unit to apply the first data signal to the first pixels, and
to subsequently apply the second data signal to the second pixels after applying the initialization signal to the first and second pixels to initialize the data-lines coupled to the first and second pixels,
the timing control unit controlling the data driver to apply the third data signal to the third pixels, and
to apply the initialization signal to the third pixels to initialize the data-lines coupled to the third pixels.

10. The device of claim 9 , wherein the timing control unit controls the scan driver to apply the scan signal to the two of the first through third pixels after at least one of the data-lines are initialized, during the one horizontal period.

11. The device of claim 9 , the timing control unit applying a plurality of switching signals to the demultiplexing unit, the initialization signal being applied to the first and second pixels when each of the plurality of switching signals simultaneously have a same low logic level as the scan signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Yang-Wan

Classifications

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3685 Primary

  Details of drivers for data electrodes · CPC title

• G09G3/30 Primary

  using electroluminescent panels · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title