Neural processing unit

Patent metadata

Field	Value
Publication number	US-9558444-B2
Application number	US-201314145711-A
Country	US
Kind code	B2
Filing date	Dec 31, 2013
Priority date	May 19, 2010
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

First claim

What is claimed is:

1. A computer-implemented method, the method being implemented by an integrated circuit on a chip, the integrated circuit including a first processor and a plurality of microengines that include a first microengine, the method comprising:
storing, in a first memory, a first block that corresponds to a first neuron and a second block that corresponds to a second neuron, wherein the first block and the second block are stored sequentially in the first memory;
obtaining, from the first memory, the first block that corresponds to the first neuron, wherein the first block includes connection information for the first neuron and an address representative of a location in a second memory, and wherein activation values matching the connection information for the first neuron are stored at the location in the second memory;
obtaining, from the second memory, the activation values matching the connection information for the first neuron;
sending, by the first processor, a packet that includes the connection information and the activation values, wherein the packet is sent to the first microengine to configure the first microengine as the first neuron; and
generating, at the first microengine, a value representative of an output of the first neuron.

2. The method of claim 1 , wherein context information for configuring the first microengine as the first neuron is stored at the first block, and wherein the context information includes the connection information and one or more of an identity of the first neuron and a basis function.

3. The method of claim 2 , wherein the packet includes at least a portion of the context information for configuring the first microengine as the first neuron.

4. The method of claim 1 , wherein the obtaining the activation values is based on at least the second address.

5. A computer-implemented method, the method being implemented by an integrated circuit on a chip, the integrated circuit including a first processor and a plurality of microengines that include a first microengine, the method comprising:
storing, in a first memory, context information corresponding to a first neuron and context information corresponding to a second neuron, wherein the context information corresponding to the first neuron and context information corresponding to the second neuron are stored sequentially in the first memory;
obtaining, from the first memory, the context information corresponding to the first neuron, wherein the context information corresponding to the first neuron includes a neuron type for the first neuron and connection information for the first neuron, wherein connection information indicates connections between the first neuron and one or more other neurons;
obtaining, from a second memory, activation values corresponding to the connections between the first neuron and the one or more other neurons;
sending, by the first processor, a packet that includes the context information and the activation values, wherein the packet is sent to the first microengine to configure the first microengine as a first neuron;
configuring, based at least on the context information and the activation values, the first microengine as the first neuron; and
generating, at the first microengine, a value representative of an output of the first neuron.

6. The method of claim 5 , wherein the context information further includes an identity of the first neuron.

7. The method of claim 5 , wherein the generating includes executing the first neuron using the activation values.

8. The method of claim 5 , further comprising:
receiving, at the first processor, a second packet including the value representative of the output of the first neuron.

9. The method of claim 5 , wherein the obtaining of the context information that corresponds to the first neuron is based on at least a first address representative of a first location in the first memory, and wherein the obtaining of the activation values is based on at least a second address representative of a second location in the second memory.

10. The method of claim 5 , wherein the first memory and the second memory are implemented in the integrated circuit.

11. A computer-implemented method, the method being implemented by an integrated circuit on a chip, the integrated circuit including a first processor and a plurality of microengines that include a first microengine and a second microengine, the method comprising:
storing, in a first memory, first context information that corresponds to a first neuron and a second context information that corresponds to a second neuron, wherein the first context information and the second context information are stored sequentially in the first memory;
obtaining, from the first memory, the first context information that corresponds to the first neuron, wherein the first context information includes a first neuron type for the first neuron, and first connection information for the first neuron, wherein the second connection information indicates a first set of connections between the first neuron and one or more other neurons;
obtaining, from the first memory, the second context information that corresponds to the second neuron, wherein the second context information includes a second neuron type for the second neuron, and second connection information for the second neuron wherein the second connection information indicates a second set of connections between the second neuron and one or more other neurons, and wherein the second set of connections includes a connection between the second neuron and the first neuron;
obtaining, from a second memory, a first set of activation values that correspond to the first set of connections;
obtaining, from the second memory, a second set of activation values that correspond to the second set of connections;
sending, by the first processor, a first packet that includes the first context information and the first set of activation values wherein the first packet is sent to the first microengine to configure the first microengine as a first neuron;
sending, by the first processor, a second packet that includes the second context information and the second set of activation values, wherein the second packet is sent to the second microengine to configure the second microengine as a second neuron;
configuring, based at least in part on the first context information and the first set of activation values, the first microengine as the first neuron;
configuring, based at least in part on the second context information and the second set of activation values, the second microengine as the second neuron;
generating, at the first microengine, a first value representative of a first output of the first neuron;
effectuating transmission of a third packet from the first microengine to the second microengine, wherein the third packet includes the first value representative of the first output of the first neuron; and
generating, at the second microengine, a second value representative of a first output of the second neuron, wherein the generating of the second value is includes using the first value as an activation value that corresponds to the connection between the second neuron and the first neuron.

12. The method of claim 11 , further comprising:
generating, by the first processor, the first packet and the second packet.

13. The method of claim 11 , wherein the generating of the second value is based on at least the second packet and the third packet, and wherein the second value is generated without accessing the first memory and/or the second memory to obtain additional information.

14. The me

Assignees

• Univ California

Inventors

• Palmer Douglas A
• Florea Michael

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/06 Primary

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06F9/06

  using stored programs, i.e. using an internal store of processing equipment to receive or retain programs · CPC title