Circuits for and methods of enabling the access to data

Patent metadata

Field	Value
Publication number	US-9558129-B2
Application number	US-201414301008-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Jun 10, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

First claim

We claim:

1. A circuit for enabling access to data, the circuit comprising:
a memory device storing data blocks having a first predetermined size;
a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size. wherein the second predetermined size of the payload data comprises a multiple N of the first predetermined size of the data blocks;
wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device; and
wherein the plurality of addresses comprises N+1 addresses and each data block other than a first data block and a last data block of the plurality of data blocks are boundary restricted.

2. The circuit of claim 1 wherein the plurality of addresses is located in a corresponding predetermined number of fields of the descriptor.

3. The circuit of claim 1 wherein the plurality of addresses comprises a memory map table to the memory device.

4. The circuit of claim 1 wherein the descriptor comprises a field having a next descriptor.

5. A circuit for enabling access to data, the circuit comprising:
a memory device storing data blocks having a first predetermined size;
a display port direct memory access circuit coupled to the memory device, the display port direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size and comprising a predetermined portion of data to be displayed, wherein the second predetermined size of the payload data comprises a multiple N of the first predetermined size of the data blocks;
a display port coupled to the display port direct memory access circuit, the display port generating the payload data;
wherein the display port direct memory access circuit accesses the data payload stored in the memory device in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device, wherein the plurality of addresses comprises N+1 addresses and each data block other than a first data block and a last data block of the plurality of data blocks are boundary restricted.

6. The circuit of claim 5 wherein the plurality of addresses is located in a predetermined number of fields of the descriptor.

7. The circuit of claim 5 wherein the plurality of addresses comprises a memory map table to the memory device.

8. The circuit of claim 5 wherein the descriptor comprises a field having a next descriptor.

9. A method of enabling access to data, the method comprising:
storing data blocks having a first predetermined size in a memory device;
receiving, at a direct memory access circuit, a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device, wherein storing the plurality of addresses comprises storing N+1 addresses;
accessing, in response to a descriptor, a data payload having the predetermined number of the data blocks corresponding to the plurality of address;
implementing a payload data size which comprises a multiple N of the first predetermined size of the data blocks; and
providing boundary restrictions for each data block other than a first data block and a last data block of the plurality of data blocks.

10. The method of claim 9 further comprising storing the plurality of addresses in a corresponding predetermined number of fields of the descriptor.

11. The method of claim 9 wherein storing the plurality of addresses comprises storing a memory map table to the memory device.

Assignees

• Xilinx Inc

Inventors

• Arbel Ygal
• Murray James J
• Kwon Hyun W
• Patel Nishit

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/30 Primary

  with priority control · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F12/145 Primary

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title