Coherence de-coupling buffer

Patent metadata

Field	Value
Publication number	US-9558116-B2
Application number	US-201414295062-A
Country	US
Kind code	B2
Filing date	Jun 3, 2014
Priority date	Apr 9, 2003
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.

First claim

What is claimed is:

1. An apparatus comprising:
a local caching agent configured to communicate with a remote source;
at least one local cache memory configured to store cache line tags and cache line data for the local caching agent;
a coherence memory configured to store the cache line tags if the cache line tags are stored in the at least one local cache memory; and
a coherence decoupling buffer coupled to the at least one local cache memory and the coherence memory and configured to store an evicted cache line tag of a cache line evicted from the at least one local cache memory in response to unavailability of space for a new cache line in the at least one local cache memory, wherein the coherence memory and the coherence decoupling buffer are configured to filter communications from the remote source to the local caching agent.

2. The apparatus of claim 1 , further comprising a main memory.

3. The apparatus of claim 2 , wherein the coherence memory is coupled to the main memory.

4. The apparatus of claim 1 , wherein the coherence memory is operable to respond to a remote snoop directed to a cache line of the at least one local cache memory, wherein the local caching agent comprises a processor, and wherein the remote snoop originates from the remote source.

5. The apparatus of claim 1 , wherein the coherence decoupling buffer is operable to respond to a remote snoop directed to an evicted cache line of the at least one local cache memory, wherein the local caching agent comprises a processor, and wherein the remote snoop originates from the remote source.

6. The apparatus of claim 1 , wherein the coherence memory is at a top of a caching hierarchy.

7. The apparatus of claim 1 , wherein the coherence decoupling buffer comprises a capacity that is of substantially less capacity than a total capacity of the at least one local cache memory.

8. An apparatus comprising:
a local caching agent configured to communicate with a remote source;
at least one local cache memory configured to store cache line tags and cache line data for the local caching agent;
a coherence memory configured to store the cache line tags if the cache line tags are stored in the at least one local cache memory and configured to filter a remote snoop from the remote source to the local caching agent; and
a coherence decoupling buffer coupled to the at least one local cache memory and the coherence memory and configured to store an evicted cache line tag of a cache line evicted from the at least one local cache memory in response to unavailability of space for a new cache line in the at least one local cache memory, wherein if the remote snoop is directed to the cache line evicted from the at least one local cache memory, the coherence decoupling buffer is configured to filter the remote snoop.

9. The apparatus of claim 8 , further comprising a main memory.

10. The apparatus of claim 9 , wherein the coherence memory is coupled to the main memory.

11. The apparatus of claim 8 , wherein the remote snoop comprises a read-only snoop, and wherein the local caching agent comprises a processor.

12. The apparatus of claim 8 , wherein the coherence memory and the coherence decoupling buffer increase cache performance.

13. The apparatus of claim 8 , wherein the coherence memory is at a top of a caching hierarchy.

14. The apparatus of claim 8 , wherein the coherence decoupling buffer comprises a capacity that is of substantially less capacity than a total capacity of the at least one local cache memory.

15. A method comprising:
filtering a remote snoop from a remote source to a local caching agent by using a coherence memory configured to store cache line tags if the cache line tags are stored in at least one local cache memory for the local caching agent configured to communicate with the remote source; and
if the remote snoop is directed to a cache line evicted from the at least one local cache memory, filtering the remote snoop by using a coherence decoupling buffer configured to store an evicted cache line tag of the cache line evicted from the at least one local cache memory in response to unavailability of space for a new cache line in the at least one local cache memory.

16. The method of claim 15 , wherein the coherence memory is coupled to a main memory.

17. The method of claim 15 , wherein the remote snoop is a read-only snoop, and wherein the local caching agent comprises a processor.

18. The method of claim 15 , wherein the coherence memory and the coherence decoupling buffer increase cache performance.

19. The method of claim 15 , wherein the coherence memory is at a top of a caching hierarchy.

20. The method of claim 15 , wherein the coherence decoupling buffer comprises a capacity that is of substantially less capacity than a total capacity of the at least one local cache memory.

Assignees

• Intellectual Ventures Holding 81 Llc

Inventors

• Rozas Guillermo J

Classifications

• G06F12/0817

  using directory methods · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title