Random number generator and method for generating random number thereof

Patent metadata

Field	Value
Publication number	US-9557964-B2
Application number	US-201414549550-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A random number generator and a method for generating random number thereof are provided. The random number generator is used for generating a random sequence and includes a linear-feedback shift register (LFSR) circuit, an oscillating circuit, a delay circuit and a logic operation circuit. The LFSR circuit receives the random sequence to generate a plurality of first control signals and a plurality of second control signals. The oscillating circuit receives the first control signals to generate a random clock signal. The delay circuit receives an alternating current signal and the second control signals to generate a random delay sampling signal. The logic operation circuit receives the random clock signal and the random delay signal to generate the random sequence.

First claim

What is claimed is:

1. A random number generator for generating a random sequence, comprising:
a linear-feedback shift register circuit, receiving the random sequence to generate a plurality of first control signals and a plurality of second control signals;
an oscillating circuit, receiving the first control signals to generate a random clock signal;
a delay circuit, receiving an alternating current signal and the second control signals to generate a random delay sampling signal; and
a logic operation circuit, receiving the random clock signal and the random delay sampling signal, so as to capture a logic level of the random clock signal based on the random delay sampling signal, and determining a logic level of an output end of the logic operation circuit based on the logic level of the random clock signal that is captured, thereby forming the random sequence,
wherein the linear-feedback shift register circuit comprises:
a plurality of flip-flop elements, each having a logic input end and a logic output end, wherein the logic output ends of the flip-flop elements are configured to provide the first control signals and the second control signals;
a plurality of logic operation elements, each having a first operation input end, a second operation input end, and an operation output end, wherein the first operation input end of the first logic operation element of the logic operation elements receives the random sequence, the second operation input end of the first logic operation element is coupled to the logic output end of the last flip-flop element of the flip-flop elements, and the operation output end of the i th logic operation element is coupled to the logic input end of the i th flip-flop element of the flip-flop elements, the logic output end of the i th flip-flop element of the flip-flop elements is coupled to the first operation input end of the i+1 th logic operation element of the logic operation elements, and i is a positive integer greater than or equal to 1; and
a plurality of switches, respectively coupled between the second operation input end of one of remaining of the logic operation elements except the first logic operation element and the logic output end of the last flip-flop element of the flip-flop elements.

2. The random number generator as claimed in claim 1 , wherein the flip-flop elements are a plurality of D flip-flops or a plurality of T flip-flops.

3. The random number generator as claimed in claim 1 , wherein the logic operation elements are respectively AND gate, OR gate, or XOR gate.

4. The random number generator as claimed in claim 1 , wherein the delay circuit comprises:
a plurality of first signal buffering elements, serially connected to each other and each receiving one of the second control signals, wherein an input end of the 1 st first signal buffering element of the first signal buffering elements receives the alternating current signal, an output end of the last first signal buffering element of the first signal buffering elements provides the random delay sampling signal.

5. The random number generator as claimed in claim 4 , wherein the first signal buffering elements are respectively one of an inverter and a buffer.

6. The random number generator as claimed in claim 1 , wherein the oscillating circuit comprises:
a plurality of second signal buffering elements, serially connected to each other and each receiving one of the first control signals, wherein an output end of one of the second signal buffering elements provides the random clock signal.

7. The random number generator as claimed in claim 6 , wherein the second signal buffering elements are respectively one of an inverter and a buffer.

8. A method for generating random numbers of a random number generator, configured for generating a random sequence, the method comprising:
receiving, by a linear-feedback shift register circuit, the random sequence to generate a plurality of first control signals and a plurality of second control signals;
receiving, by an oscillating circuit, the first control signals to generate a random clock signal;
receiving, by a delay circuit, an alternating current signal and the second control signals to generate a random delay sampling signal; and
receiving, by a logic operation circuit, the random clock signal and the random delay sampling signal, so as to capture a logic level of the random clock signal based on the random delay sampling signal, wherein the logic operation circuit determines a logic level of an output end of the logic operation circuit based on the logic level of the random clock signal that is captured, thereby forming the random sequence,
wherein the linear-feedback shift register circuit comprises:
a plurality of flip-flop elements, each having a logic input end and a logic output end, wherein the logic output ends of the flip-flop elements are configured to provide the first control signals and the second control signals;
a plurality of logic operation elements, each having a first operation input end, a second operation input end, and an operation output end, wherein the first operation input end of the first logic operation element of the logic operation elements receives the random sequence, the second operation input end of the first logic operation element is coupled to the logic output end of the last flip-flop element of the flip-flop elements, and the operation output end of the i th logic operation element is coupled to the logic input end of the i th flip-flop element of the flip-flop elements, the logic output end of the i th flip-flop element of the flip-flop elements is coupled to the first operation input end of the i+1 th logic operation element of the logic operation elements, and i is a positive integer greater than or equal to 1; and
a plurality of switches, respectively coupled between the second operation input end of one of remaining of the logic operation elements except the first logic operation element and the logic output end of the last flip-flop element of the flip-flop elements.

9. The method for generating random numbers of the random number generator as claimed in claim 8 , wherein a part of the first control signals are completely identical to a part of the second control signals.

10. The method for generating random numbers of the random number generator as claimed in claim 9 , wherein the first control signals are completely identical to the second control signals.

11. The method for generating random numbers of the random number generator as claimed in claim 8 , wherein the first control signals are completely different from the second control signals.

12. The method for generating random numbers of the random number generator as claimed in claim 8 , wherein the alternating current signal is one of a sine wave signal, a triangular wave signal, a square wave signal, or a saw tooth wave signal.

Assignees

• Winbond Electronics Corp

Inventors

• Lee Chen-Yi

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F7/584

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• H03K3/356

  Bistable circuits · CPC title