Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power

Patent metadata

Field	Value
Publication number	US-9557797-B2
Application number	US-201414319393-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	May 20, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

First claim

What is claimed is:

1. A method for selecting processor cores of a multi-core processor within a computing device, comprising:
determining a state of the computing device;
determining a plurality of ratios of current leakage by comparing a current leakage of each of a plurality of processor cores to current leakages of other processor cores of the plurality of processor cores;
comparing the plurality of ratios of current leakage to a plurality of boundary values corresponding to the state of the computing device in a plurality of inequalities;
selecting a processor core associated with at least two boundary values in response to determining that at least two of the plurality of inequalities are true; and
engaging the selected processor core to execute a task in combination with another processor core.

2. The method of claim 1 , wherein:
determining the plurality of ratios of current leakage by comparing the current leakage of each of the plurality of processor cores to current leakages of other processor cores of the plurality of processor cores comprises:
determining a first ratio of a current leakage by comparing a current leakage of a first processor core to a current leakage of a second processor core; and
determining a second ratio of current leakage by comparing a current leakage of a third processor core to the current leakage of the second processor core;

comparing the plurality of ratios of current leakage to the plurality of boundary values corresponding to the state of the computing device in the plurality of inequalities comprises:
comparing the first ratio to a first boundary value corresponding to the state of the computing device in a first inequality; and
comparing the second ratio of current leakage to a second boundary value corresponding to the state of the computing device in a second inequality; and

selecting the processor core associated with the at least two boundary values in response to determining that the at least two of the plurality of inequalities are true comprises selecting a preferred processor core associated with the first boundary value and the second boundary value in response to determining that the first inequality and the second inequality are true.

3. The method of claim 1 , further comprising:
storing a plurality of boundary values each associated with a state of the computing device and a set of processor cores determined to be preferred for use during the state of the computing device; and
loading the plurality of boundary values for the state of the computing device.

4. The method of claim 1 , further comprising retrieving the current leakage of the plurality of processor cores from a storage device of the multi-core processor.

5. The method of claim 1 , wherein selecting the processor core associated with the at least two boundary values in response to determining that the at least two of the plurality of inequalities are true comprises:
retrieving a plurality of sets of processor cores associated with the at least two boundary values;
comparing each of the plurality of sets of processor cores with other sets within the plurality of sets of processor cores; and
selecting the processor core that is present in at least two sets of processor cores within the plurality of sets of processor cores.

6. The method of claim 1 , wherein determining the state of the computing device comprises selecting a current state of the computing device or a predicted state of the computing device.

7. The method of claim 1 , further comprising composing a processor core bring-up sequence wherein the selected processor core is next in the processor core bring-up sequence.

8. The method of claim 1 , wherein determining the plurality of ratios of current leakage by comparing the current leakage of each of the plurality of processor cores to current leakages of other processor cores of the plurality of processor cores comprises:
expressing the plurality of ratios of current leakage as ratios of static current leakage in a digital domain at a quiescent state (IDDq) for each of the plurality of processor cores such that the plurality of ratios of current leakage include IDDq i+1 /IDDq i , IDDq i+2 /IDDq i , IDDq i+3 /IDDq i , IDDq i+4 /IDDq i , IDDq n /IDDq i .

9. A computing device, comprising:
a processor configured with processor-executable instructions to perform operations comprising:
determining a state of the computing device;
determining a plurality of ratios of current leakage by comparing a current leakage of each of a plurality of processor cores to current leakages of other processor cores of the plurality of processor cores;
comparing the plurality of ratios of current leakage to a plurality of boundary values corresponding to the state of the computing device in a plurality of inequalities;
selecting a processor core associated with at least two boundary values in response to determining that at least two of the plurality of inequalities are true; and
engaging the selected processor core to execute a task in combination with another processor core.

10. The computing device of claim 9 , wherein the processor is further configured with processor-executable instructions to perform operations such that:
determining the plurality of ratios of current leakage by comparing the current leakage of each of the plurality of processor cores to current leakages of other processor cores of the plurality of processor cores comprises:
determining a first ratio of a current leakage by comparing a current leakage of a first processor core to a current leakage of a second processor core; and
determining a second ratio of current leakage by comparing a current leakage of a third processor core to the current leakage of the second processor core;

comparing the plurality of ratios of current leakage to the plurality of boundary values corresponding to the state of the computing device in the plurality of inequalities comprises:
comparing the first ratio to a first boundary value corresponding to the state of the computing device in a first inequality; and
comparing the second ratio of current leakage to a second boundary value corresponding to the state of the computing device in a second inequality; and

selecting the processor core associated with the at least two boundary values in response to determining that the at least two of the plurality of inequalities are true comprises selecting a preferred processor core associated with the first boundary value and the second boundary value in response to determining that the first inequality and the second inequality are true.

11. The computing device of claim 9 , further comprising a memory communicatively connected to the processor, and wherein the processor is further configured with processor-executable instructions to perform operations further comprising:
storing a plurality of boundary values each associated with a state of the computing device and a set of processor cores determined to be preferred for use during the state of the computing device in the memory; and
loading the plurality of boundary values for the state of the computing device from the memory.

12. The computing device of claim 9 , further comprising a storage device communicatively connected to the processor, and wherein the processor is further configured with processor-executable instructions to perform operations further comprising retrieving the current leakage of the plurality of processor cores from the storage device.

13. The computing device of claim 9 , wherein the processor is further configured with processor-executable instructions to perform operations such that selecti

Assignees

• Qualcomm Inc

Inventors

• Mittal Rajat
• Saeidi Mehdi
• Xue Tao
• Alton Ronald Frank
• Chandra Rajit
• Dasnurkar Sachin

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/329

  by task scheduling · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title