Layered body with support substrate, method for fabricating same, and method for fabricating multi-layer wiring substrate

Patent metadata

Field	Value
Publication number	US-9554456-B2
Application number	US-201314655472-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 28, 2012
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A layered body with a support substrate, the layered body being on the support substrate and comprising: metal foil B which is arranged on the support substrate and on which a wiring pattern is not formed; an insulating layer B which is arranged on the metal foil B; metal foil C which is arranged on the insulating layer B and on which a wiring pattern is not formed; non-through holes for a product and non-through holes for an alignment mark that penetrate the metal foil C and the insulating layer B and reach the metal foil B; and the alignment mark of a dot pattern in which the non-through holes for the alignment mark are filled by plating and gathered and arranged in an individually independent state.

First claim

The invention claimed is:

1. A layered body with a support substrate, the layered body being on the support substrate and comprising:
metal foil B arranged on the support substrate;
an insulating layer B arranged on the metal foil B;
metal foil C arranged on the insulating layer B;
a non-through hole for a product and non-through holes for an alignment mark that penetrate the metal foil C and the insulating layer B and reach the metal foil B; and
the alignment mark of a dot pattern in which the non-through holes for the alignment mark are filled by plating and gathered and arranged in an individually independent state.

2. The layered body with the support substrate according to claim 1 ,
wherein the alignment mark is the dot pattern in which the non-through holes for the alignment mark are gathered and arranged in a multiple ring shape in the individually independent state.

3. The layered body with the support substrate according to claim 1 ,
wherein the support substrate includes an insulating layer A and metal foil A, and
wherein the layered body includes the metal foil B which is arranged directly on the metal foil A and is one size smaller than the metal foil A, the insulating layer B which is one size larger than the metal foil B, the metal foil C arranged on the insulating layer B, and the non-through hole for the product and the non-through holes for the alignment mark that penetrate the metal foil C and the insulating layer B and reach the metal foil B.

4. A method for fabricating the layered body with the support substrate according to claim 1 , the method comprising:
a step (a) of piling up, on metal foil A of the support substrate, metal foil B one size smaller than the metal foil A, an insulating layer B one size larger than the metal foil B, and metal foil C in this order, and heating, pressurizing, laminating and integrating them;
a step (b) of forming a non-through hole for a product and non-through holes for an alignment mark of a dot pattern from the metal foil C to the metal foil B by penetrating the metal foil C and the insulating layer B by a laser; and
a step (c) of filling the non-through hole for the product and the non-through holes for the alignment mark by plating.

5. A method for fabricating a multi-layer wiring substrate comprising:
after the step (c) in claim 4 ,
a step (d) of separating the support substrate and the layered body;
a step (e) of forming a guide hole for positioning of a wiring pattern with non-through holes for an alignment mark of a dot pattern filled with plating on the separated layered body as a reference;
a step (f) of forming etching resist with the guide hole as a reference; and
a step (g) of forming the wiring pattern by etching the metal foil B or C.

6. A layered product comprising:
a support substrate; and
a layered body arranged on the substrate, wherein the layered body comprising:
first metal foil arranged on the support substrate;
an first insulating layer arranged on the first metal foil;
second metal foil arranged on the first insulating layer;
a non-through hole for a product and non-through holes for an alignment mark that penetrate the second metal foil and the first insulating layer and reach the first metal foil; and
the alignment mark of a dot pattern in which the non-through holes for the alignment mark are filled by plating and gathered and arranged in an individually independent state.

7. The layered product according to claim 6 ,
wherein the alignment mark is the dot pattern in which the non-through holes for the alignment mark are gathered and arranged in a multiple ring shape in the individually independent state.

8. The layered product according to claim 6 ,
wherein the support substrate comprises an second insulating layer and third metal foil, and
wherein the first metal foil of the layered body is arranged directly on the third metal foil of the support substrate and is smaller than the third metal foil, and the first insulating layer is larger than the first metal foil.

9. A method for fabricating the layered product of claim 8 , the method comprising:
piling up the first metal foil, the first insulating layer, and the second metal foil above the third metal foil of the support substrate in this order, and heating, pressurizing, laminating and integrating them;
forming the non-through hole for a product and the non-through holes for the alignment mark of the dot pattern from the second metal foil to the first metal foil by penetrating the second metal foil and the first insulating layer by a laser; and
filling the non-through hole for the product and the non-through holes for the alignment mark by plating.

10. A method for fabricating a multi-layer wiring substrate comprising:
providing the layered product of claim 8 ;
separating the support substrate and the layered body of the layered product after the providing;
forming a guide hole for positioning of a wiring pattern with the non-through holes for the alignment mark of the dot pattern filled with plating on the separated layered body as a reference;
forming etching resist with the guide hole as a reference; and
forming the wiring pattern by etching at least one of the first and second metal foil.

Assignees

• Hitachi Chemical Co Ltd

Inventors

• HATAZAWA Hiroki

Classifications

• H05K3/4652

  Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence) · CPC title

• H05K3/22

  Secondary treatment of printed circuits {(H05K3/1283 takes precedence; embedding circuits in grooves by pressure H05K3/107)} · CPC title

• H05K2201/09063

  Holes or slots in insulating substrate not used for electrical connections · CPC title

• H05K1/0269 Primary

  for visual or optical inspection · CPC title

• H05K2201/09918

  Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components · CPC title