GOA circuit based on LTPS semiconductor TFT

Patent metadata

Field	Value
Publication number	US-9553577-B2
Application number	US-201514422694-A
Country	US
Kind code	B2
Filing date	Feb 6, 2015
Priority date	Nov 3, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part ( 100 ), a pull-up part ( 200 ), a first pull-down part ( 400 ) and a pull-down holding part ( 500 ); the pull-down holding part ( 500 ) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS 1 , VSS 2 , VSS 3 ) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the functioning period can be solved to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

First claim

What is claimed is:

1. A gate drive on array (GOA) circuit based on low temperature polycrystalline silicon (LTPS) semiconductor thin film transistor (TFT), comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part, a pull-up part, a first pull-down part and a pull-down holding part;
the pull-up control part comprises a first transistor, and both a gate and a source are electrically coupled to an output end of an N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node;
the pull-up part comprises a second transistor, and a gate thereof is electrically coupled to the first node, and a source is electrically coupled to a first clock driving signal, and a drain is electrically coupled to an output end;
the pull-down holding part is electrically coupled to the first node, the output end, a DC constant high voltage level, and a first, a second and a third DC constant low voltage levels;
the pull-down holding part utilizes a high/low voltage reverse design and comprises:
a third transistor, and both a gate and a source of the third transistor are electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to a source of a fifth transistor;
a fourth transistor, and a gate of the fourth transistor is electrically coupled to the drain of the third transistor, and a source is electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to a second node;
the fifth transistor, and a gate of the fifth transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the third transistor, and a drain is electrically coupled to the first DC constant low voltage level;
a sixth transistor, and a gate of the sixth transistor is electrically coupled to the first node, and a source is electrically coupled to the second node, and a drain is electrically coupled to a source of an eighth transistor;
the eighth transistor, and the gate of the eighth transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the sixth transistor, and a drain is electrically coupled to the third DC constant low voltage level;
the tenth transistor, and the gate of the tenth transistor is electrically coupled to the second node and a source is electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to the drain of the sixth transistor;
a twelfth transistor, and a gate of the twelfth transistor is electrically coupled to the second node, and a drain is electrically coupled to the first node, and a source is electrically coupled to the second DC constant low voltage level;
a thirteenth transistor, and a gate of the thirteenth transistor is electrically coupled to the second node, and a drain is electrically coupled to the output end, and a source is electrically coupled to the first DC constant low voltage level;
the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, provide positive high voltage levels, employed to control activations of the twelfth transistor and the thirteenth transistor; the eighth transistor constructs a reverse bootstrap of negative voltage level in a functioning period, employed to provide a lower voltage level to the second node in the functioning period; the DC constant high voltage level is utilized to provide a proper high voltage level to the second node in a non-functioning period to maintain the first node and the output end at low voltage level;
the first pull-down part is electrically coupled to the first node, a second clock driving signal and the second DC constant low voltage level, and the pull-down part pulls down a voltage level of the first node to the second DC constant low voltage level according to the second clock driving signal;
the first pull-down part comprises a fourteenth transistor, and a gate of the fourteenth transistor is electrically coupled to the second clock driving signal, and a source is electrically coupled to the first node, and a drain is electrically coupled to the second DC constant low voltage level;
the third DC constant low voltage level<the second DC constant low voltage level<the first DC constant low voltage level.

2. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , wherein the pull-down holding part further comprises a ninth transistor, and a gate of the ninth transistor is coupled to the first node, and a source is electrically coupled to the gate of the tenth transistor, and a drain is electrically coupled to the third DC constant low voltage level; an eleventh transistor, and both a gate and a source of the eleventh transistor are electrically coupled to the DC constant high voltage level, and a drain is electrically coupled to the gate of the tenth transistor; the gate of the tenth transistor is disconnected with the second node.

3. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , wherein the fourth transistor, the sixth transistor and the eighth transistor are coupled in series.

4. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , further comprises a boost part, and the boost part is electrically coupled between the first node and the output end, employed to boost voltage level of the first node.

5. The GOA circuit based on LTPS semiconductor TFT according to claim 4 , wherein the boost part comprises a capacitor, and one end of the capacitor is electrically coupled to the first node, and the other end is electrically coupled to the output end.

6. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , wherein waveform duty ratios of the first clock driving signal and the second clock driving signal are smaller than 50/50; the fourteenth transistor pulls down the voltage level of the first node to the second DC constant low voltage level in a high voltage level period of the second clock driving signal.

7. The GOA circuit based on LTPS semiconductor TFT according to claim 4 , wherein a signal output waveform of the first node changes according to the variation of the waveform duty ratios of the first clock driving signal and the second clock driving signal.

8. The GOA circuit based on LTPS semiconductor TFT according to claim 7 , wherein a signal output waveform of the first node appears to be convex.

9. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , wherein in the first level connection of the GOA circuit, both the gate and the drain of the first transistor are electrically coupled to an activation signal end of the circuit.

10. The GOA circuit based on LTPS semiconductor TFT according to claim 1 , wherein the GOA circuit employs an output signal of the output end as being a former-latter level transfer signal.

11. A gate drive on array (GOA) circuit based on low temperature polycrystalline silicon (LTPS) semiconductor thin film transistor (TFT), comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part, a pull-up part, a first pull-down part and a pull-down holding part;
the pull-up control part comprises a first transistor, and both a gate and a source thereof are electrically coupled to an output end of an N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node;
the pull-up part comprises a second transistor, and a gate of the second transistor is electrically coupled to the first node, and a source is electrically couple

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Xiao Juncheng

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G06F3/01

  Input arrangements or combined input and output arrangements for interaction between user and computer (G06F3/16 takes precedence) · CPC title