Power converter with pre-compensation for dead-time insertion

Patent metadata

Field	Value
Publication number	US-9553540-B2
Application number	US-201514601300-A
Country	US
Kind code	B2
Filing date	Jan 21, 2015
Priority date	Jan 21, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A power converter has a phase leg with upper and lower switching devices coupled across a DC link. A junction between the devices is coupled to a load. A current sensor detects direction of current flow from the junction to the load. A gate driver activates the devices according to upper and lower gate signals in response to pulse-width modulation (PWM) to generate nominal gate signals from a variable duty cycle. When the positive current direction is detected then the upper gate signal has turn-on and turn-off times shifted by a predetermined offset with respect to the nominal signals, and dead-times are added to the lower gate signals. When the negative direction is detected then the lower gate signal has turn-on and turn-off times shifted by the predetermined offset with respect to the nominal signals, and dead-times are added to the upper gate signals.

First claim

What is claimed is:

1. A power converter comprising:
a DC link configured to receive a DC supply voltage;
a phase leg comprising an upper switching device and a lower switching device coupled across the DC link, wherein a junction between the upper and lower switching devices is configured to be coupled to a load;
a current sensor for the phase leg detecting a positive or negative direction of a current flow from the junction to the load; and
a gate driver coupled to the phase leg activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal in response to pulse-width modulation (PWM) to generate nominal gate signals from a variable duty cycle;
wherein when the positive current direction is detected then the upper gate signal has a turn-on time and a turn-off time each shifted by a predetermined offset with respect to the nominal gate signals, and the lower gate signal has a turn-on time delayed with respect to a corresponding turn-off time of the upper gate signal and has a turn-off time advanced with respect to a corresponding turn-on time of the upper gate signal; and
wherein when the negative current direction is detected then the lower gate signal has a turn-on time and a turn-off time each shifted by a predetermined offset with respect to the nominal gate signals, and the upper gate signal has a turn-on time delayed with respect to a corresponding turn-off time of the lower gate signal and has a turn-off time advanced with respect to a corresponding turn-on time of the lower gate signal.

2. The power converter of claim 1 wherein the upper and lower gate signals for both the positive and negative current directions are continuously generated, and wherein the corresponding gate signals are selected for the gate driver in response to the detected current direction.

3. The power converter of claim 1 wherein the pulse-width modulation includes a PWM carrier signal, wherein the upper and lower gate signals are generated when the positive current direction is detected by comparing the PWM carrier signal with a positive offset from the variable duty cycle, and wherein the upper and lower gate signals are generated when the negative current direction is detected by comparing the PWM carrier signal with a negative offset from the variable duty cycle.

4. The power converter of claim 3 wherein the gate signals are generated by AND-gating each of the comparison signals with a respective delayed comparison signal, wherein the delayed comparison signals are delayed according to a predetermined dead-time t D .

5. The power converter of claim 3 wherein the carrier signal has a predetermined slope, and wherein a difference between the positive offset and the negative offset divided by the predetermined slope is equal to the predetermined dead-time t D .

6. The power converter of claim 5 wherein the carrier signal is comprised of a triangle waveform.

7. The power converter of claim 1 further comprising:
a second phase leg comprising a second upper switching device and a second lower switching device coupled across the DC link, wherein a second junction between the second upper and lower switching devices is configured to be coupled to the load;
a second current sensor for the second phase leg detecting a positive or negative direction of a second current flow from the second junction to the load; and
a second gate driver coupled to the second phase leg activating the second upper switching device according to a second upper gate signal and activating the second lower switching device according to a second lower gate signal in response to a second PWM carrier signal to generate nominal second gate signals from the variable duty cycle;
wherein when the positive second current direction is detected then the second upper gate signal has a turn-on time and a turn-off time each shifted by the predetermined offset with respect to the nominal second gate signals, and the second lower gate signal has a turn-on time delayed with respect to a corresponding turn-off time of the second upper gate signal and has a turn-off time advanced with respect to a corresponding turn-on time of the second upper gate signal; and
wherein when the negative second current direction is detected then the second lower gate signal has a turn-on time and a turn-off time each shifted by a second predetermined offset with respect to the nominal second gate signals, and the second upper gate signal has a turn-on time delayed with respect to a corresponding turn-off time of the second lower gate signal and has a turn-off time advanced with respect to a corresponding turn-on time of the second lower gate signal.

8. The power converter of claim 1 wherein the load is comprised of an electric traction motor for a road vehicle, and wherein the variable duty cycle corresponds to a desired torque from the traction motor.

9. A method controlling a power converter comprising:
generating pulse-width modulated (PWM) upper and lower gate signals for driving respective switching devices in a phase leg;
detecting a current direction from the phase leg to a load;
when the direction is positive, inserting a dead-time equally delaying both turn-on and turn-off in the upper gate signal and delaying turn-on and advancing turn-off in the lower gate signal.

10. The method of claim 9 further comprising the step of:
when the direction is negative, inserting a dead-time equally delaying both turn-on and turn-off in the lower gate signal and delaying turn-on and advancing turn-off in the upper gate signal.

11. The method of claim 10 wherein the inserting steps are comprised of:
comparing a PWM carrier signal with a positive offset from a variable PWM duty cycle to generate a first comparison signal;
comparing the PWM carrier signal with a negative offset from the variable PWM duty cycle to generate a second comparison signal; and
AND-gating each of the comparison signals with a respective delayed comparison signal, wherein the delayed comparison signals are delayed according to a predetermined dead-time t D .

12. The method of claim 11 wherein the carrier signal has a predetermined slope, and wherein a difference between the positive offset and the negative offset divided by the predetermined slope is equal to the predetermined dead-time t D .

13. The method of claim 10 wherein the carrier signal is comprised of a triangle waveform.

14. A power converter comprising:
a DC link configured to receive a DC supply voltage;
a phase leg comprising an upper switching device and a lower switching device coupled across the DC link, wherein a junction between the upper and lower switching devices is configured to be coupled to a load;
a current sensor for the phase leg detecting a positive or negative direction of a current flow from the junction to the load; and
a gate driver coupled to the phase leg activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal; and
a controller 1) generating positive and negative duty cycle offsets from a commanded duty cycle, 2) comparing a PWM carrier signal to the duty cycle offsets to generate first and second comparison signals, 3) AND-gating the comparison signals with respective delayed comparison signals to generate positive and negative pre-compensated gate drive signals, wherein the delayed comparison signals are delayed according to a predetermined dead-time t D , 4) selecting the positive pre-compensated gate drive signal when the direction is positive, and 5) selecting the negati

Assignees

• Ford Global Tech Llc

Inventors

• Degner Michael W
• Chen Chingchi
• Kikuchi Jun

Classifications

• H02M7/5387 Primary

  in a bridge configuration · CPC title

• H02M5/458

  using semiconductor devices only · CPC title

• H02P27/04

  using variable-frequency supply voltage, e.g. inverter or converter supply voltage · CPC title

• G01R19/0092

  Measuring current only · CPC title

• H02P27/08 Primary

  with pulse width modulation · CPC title