Active bridge back powering protection and powered device interface with active bridge control

Patent metadata

Field	Value
Publication number	US-9553525-B2
Application number	US-201314033612-A
Country	US
Kind code	B2
Filing date	Sep 23, 2013
Priority date	Sep 27, 2012
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A method is disclosed to at least partially prevent back powering of power sourcing equipment. In one or more implementations, the method includes detecting a magnitude of current through a current sensor, such as a transistor and/or a resistor. The active FET bridge is configured to rectify input power supplied by power sourcing equipment to a power over Ethernet (PoE) powered device. The method also includes causing the transistor to transition from a closed configuration to an open configuration to at least substantially prevent current flow through the transistor when the magnitude of current is below a predefined threshold to at least substantially prevent back powering of the PSE.

First claim

What is claimed is:

1. An active bridge system, comprising:
at least one field-effect transistor comprising a portion of an active field-effect bridge, the at least one field-effect transistor configured to detect a magnitude of current;
active bridge control circuitry integrated within a powered device interface controller, the active bridge control circuitry operatively connected to the at least one field-effect transistor, the active bridge control circuitry configured to turn off the at least one field-effect transistor when a negative current is detected by the at least one field-effect transistor to prevent back powering of power sourcing equipment,
where the active bridge field-effect bridge is configured to rectify input power supplied by power sourcing equipment to a Power over Ethernet powered device.

2. The active bridge system of claim 1 , wherein the at least one field-effect transistor comprises an n-type field-effect transistor.

3. The active bridge system of claim 1 , wherein the at least one field-effect transistor comprises a p-type field-effect transistor.

4. The active bridge system of claim 1 , wherein the active bridge system is located before the Power over Ethernet powered device.

5. The active bridge system of claim 1 , wherein the Power over Ethernet powered device includes an RJ45 connector.

6. A method comprising:
detecting a magnitude of current through at least one field-effect transistor comprising a portion of an active field-effect bridge; and
causing the at least one field-effect transistor to transition from a closed configuration to an open configuration to at least substantially prevent current flow through the at least one field-effect transistor with active bridge control circuitry integrated within a powered device interface controller when the magnitude of current is negative to at least substantially prevent back powering of power sourcing equipment,
wherein the active field-effect bridge is configured to rectify input power supplied by the power sourcing equipment to a Power over Ethernet powered device, wherein the at least one field-effect transistor is directly connected to the power sourcing equipment.

7. The method of claim 6 , wherein causing the at least one field-effect transistor to transition from the closed configuration to the open configuration comprises causing at least one n-type field effect transistor to transition.

8. The method of claim 6 , wherein causing the at least one field-effect transistor to transition from the closed configuration to the open configuration comprises causing at least one p-type field effect transistor to transition.

9. The method of claim 6 , wherein the active bridge system comprises is located before the Power over Ethernet device.

10. The method of claim 6 , wherein the Power over Ethernet powered device includes an RJ45 connector.

11. A method comprising:
determining a polarity of an input voltage between a first terminal and a second terminal at an input of an active field-effect bridge for a power over Ethernet (PoE) powered device controller, where the polarity is determined using a powered device interface controller;
causing, by way of active bridge control circuitry integrated within the powered device interface controller, a first transistor and a second transistor to transition from an open configuration to a closed configuration when the polarity at the input of the active field-effect bridge is positive and the input voltage is greater than an activation threshold while causing a third transistor and a fourth transistor to at least one of remain in an open configuration or transition from a closed configuration to an open configuration; and
causing the third transistor and the fourth transistor, by way of the active bridge control circuitry integrated within the powered device interface controller, to transition from an open configuration to a closed configuration when the polarity at the input of the active field-effect bridge is negative and the input voltage is greater than an activation threshold while causing the first transistor and the second transistor to at least one of remain in an open configuration or transition from a closed configuration to an open configuration to prevent back powering of power sourcing equipment,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are included in the active field-effect transistor (FET) bridge, the active FET bridge configured to rectify input power supplied by power source equipment (PSE) to a PoE powered device, the powered device interface controller operatively connected to the active field-effect transistor bridge, wherein the active FET bridge is directly connected to the power sourcing equipment.

Assignees

• Maxim Integrated Products

Inventors

• Huynh Thong A
• Zou Gaoling
• Vigna Andrea
• Ranzato Mauro
• Mariano Gianluca

Classifications

• H02M7/219 Primary

  in a bridge configuration · CPC title

• H02M2007/2195

  Electricity · mapped topic

• H02M2001/0009

  Electricity · mapped topic

• H02M7/06 Primary

  using discharge tubes without control electrode or semiconductor devices without control electrode · CPC title

• Y02B70/1408

  Cross-Sectional Technologies · mapped topic