Method of integration of a magnetoresistive structure

US9553260B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9553260-B2
Application numberUS-201514704915-A
CountryUS
Kind codeB2
Filing dateMay 5, 2015
Priority dateDec 17, 2010
Publication dateJan 24, 2017
Grant dateJan 24, 2017

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  1. Title

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising: depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) on a portion of the first surface of the first dielectric layer; etching the first conductive material wherein, after etching, a portion of the first conductive material remains (i) in the via (ii) and on the first surface of the first dielectric layer; depositing a second conductive material in the via and on the first conductive material remaining in the via; depositing a first electrode material on the second conductive material which is in the via; polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material which is in the via, (ii) over the first conductive material which is in the via, and (iii) over the portion of the first surface of the first dielectric layer; and forming a magnetoresistive structure on the first electrode material. 2. The method of claim 1 wherein depositing the first conductive material, etching the first conductive material, and depositing the second conductive material are performed in-situ. 3. The method of claim 1 wherein: the first conductive material comprises tantalum or tantalum-nitride, and the first electrode material comprises tantalum or tantalum-nitride. 4. The method of claim 1 wherein the magnetoresistive structure is a magnetic bit. 5. A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising: depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) on a portion of the first surface of the first dielectric layer; etching the first conductive material wherein, after etching, a portion of the first conductive material remains (i) in the via (ii) and on the first surface of the first dielectric layer; depositing a second conductive material (i) in the via and on the first conductive material remaining in the via and (ii) over a portion of the first surface of the first dielectric layer; depositing a first electrode material (i) on the second conductive material which is in the via and (ii) over a portion of the first surface of the first dielectric layer; polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material which is in the via and (ii) over the first conductive material which is in the via; and forming a magnetoresistive structure on the first electrode material. 6. The method of claim 5 wherein depositing the first conductive material, etching a portion of the first conductive material, and depositing the second conductive material are performed in-situ. 7. The method of claim 5 wherein: the first conductive material comprises tantalum or tantalum-nitride, and the first electrode material comprises tantalum or tantalum-nitride. 8. The method of claim 5 wherein the magnetoresistive structure is a magnetic bit. 9. The method of claim 5 wherein forming the first conductive material consists of forming one of tungsten or ruthenium. 10. A method of manufacturing one or more interconnects to magnetoresistive structure, the method comprising: depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) on a portion of the first surface of the first dielectric layer; etching the first conductive material before depositing a second conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) on the first surface of the first dielectric layer; depositing the second conductive material (i) over the portion of the first surface of the first dielectric layer and (ii) on the first conductive material which is in the via; depositing a first electrode material (i) over the portion of the first surface of the first dielectric layer and (ii) on the second conductive material which is in the via; polishing the first electrode material wherein, after polishing, the first electrode material is (i) over the portion of the first surface of the first dielectric layer and (ii) on the second conductive material which is in the via; and forming a magnetoresistive structure on the first electrode material. 11. The method of claim 10 wherein: the first conductive material comprises tantalum or tantalum-nitride, and the first electrode material comprises tantalum or tantalum-nitride. 12. The method of claim 11 wherein depositing the first conductive material, etching the first conductive material, and depositing the second conductive material are performed in-situ. 13. The method of claim 10 wherein depositing the first conductive material, etching the first conductive material, and depositing the second conductive material are performed in-situ. 14. A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising: depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) on a portion of the first surface of the first dielectric layer; etching the first conductive material wherein, after etching, a portion of the first conductive material remains (i) in the via and (ii) on the first surface of the first dielectric layer; depositing a second conductive material in the via and on the first conductive material remaining in the via; depositing a first electrode material (i) over the first conductive material which is in the via and (ii) on the second conductive material which is in the via; and forming a magnetoresistive structure on the first electrode material. 15. The method of claim 14 wherein depositing the first conductive material, etching a portion of the first conductive material, and depositing the second conductive material are performed in-situ. 16. The method of claim 14 wherein: the first conductive material comprises tantalum or tantalum-nitride, and the first electrode material comprises tantalum or tantalum-nitride. 17. The method of claim 14 wherein the magnetoresistive structure is a magnetic bit. 18. The method of claim 17 wherein depositing the first conductive material, etching the first conductive material, and depositing the second conductive material are performed in-situ.

Assignees

Inventors

Classifications

  • by chemical means · CPC title

  • the conductive layers comprising transition metals · CPC title

  • by smoothing the dielectric parts · CPC title

  • by smoothing of conductive parts, e.g. by planarisation · CPC title

  • H10W20/056Primary

    by filling conductive material into holes, grooves or trenches · CPC title

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What does patent US9553260B2 cover?
A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.
Who is the assignee on this patent?
Everspin Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/056. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).