Process for manufacturing a semiconductor device comprising an empty trench structure and semiconductor device manufactured thereby

Patent metadata

Field	Value
Publication number	US-9553209-B2
Application number	US-201514856148-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Nov 18, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench.

First claim

The invention claimed is:

1. A process for manufacturing a microelectronic semiconductor device, the process comprising:
selectively etching a body to form a trench having side walls and an open end, the selectively etching forming reaction by-products;
causing the reaction by-products to deposit on the side walls of the trench to form a restriction element in proximity of the open end of the trench; and
forming a metal layer above the body, the metal layer closing the open end of the trench without penetrating into the trench.

2. The process according to claim 1 , wherein causing the reaction by-products to deposit on walls of the trench comprises forming a passivation layer on the side walls of the trench, the passivation layer forming the restriction element in proximity of the open end of the trench.

3. The process according to claim 1 , wherein selectively etching comprises carrying out a dry RIE with flows of gas comprising CF 4 and CHF 3 , wherein the flow of CF 4 is greater than the flow of CHF 3 .

4. The process according to claim 3 , wherein the flow of CF 4 is 2 to 4 times the flow of CHF 3 .

5. The process according to claim 3 , wherein selectively etching comprises using a magnetic-confinement etching machine.

6. The process according to claim 1 , wherein selectively etching the body to form the trench comprises forming a mask of metal material covering the body and having an opening and selectively removing the body through the opening of the mask.

7. The process according to claim 6 , wherein the metal layer is deposited above the mask and forms a tip-shaped portion within the opening.

8. The process according to claim 1 , wherein the body comprises a substrate of semiconductor material and at least one insulating layer above the substrate, and selectively etching comprises removing portions of the insulating layer.

9. The process according to claim 1 , wherein the body comprises a substrate of semiconductor material and a stack of layers overlying the substrate, and selectively etching the body comprises selectively etching the stack of layers using an etching solution.

10. The process according to claim 1 , wherein forming the metal layer is carried out in vacuum conditions to obtain an integrated microminiature vacuum-tube device.

11. The process according to claim 1 , wherein selectively etching comprises a pre-etching and a washing step.

12. A vacuum microelectronic device comprising:
a semiconductor body;
a trench etched in the semiconductor body, the trench having side walls and an open end;
a restriction element at an open end of the trench, the restriction element formed by reaction by-products, at least some of the reaction by-products being formed on the side walls of the trench; and
a metal layer above the semiconductor body, the metal layer closing the open end of the trench without penetrating into the trench.

13. The vacuum microelectronic device according to claim 12 , further comprising at least one insulating layer over the semiconductor body, the insulating layer having a through opening aligned with the trench, the restriction element being in the through opening.

14. The vacuum microelectronic device according to claim 12 , wherein the restriction element has a first thickness at the open end of the trench, the restriction element being on the sidewalls of the trench and having a second thickness that is less than the first thickness.

15. The vacuum microelectronic device according to claim 12 , wherein the restriction element is a passivation layer.

16. The vacuum microelectronic device according to claim 12 , wherein the metal layer is a cathode layer.

17. A process comprising:
forming a mask layer over a stack of layers, the mask layer including at least one through opening having side walls;
etching the stack of layers through the at least one through opening of the mask layer to form a trench, the trench having side walls and an open end, wherein etching causes reaction by-products to be deposited on the side walls of the trench and the side walls of the mask layer to form a restriction element; and
forming a metal layer covering mask layer and the stack of layers, the metal layer closing the open end of the trench without penetrating into the trench.

18. The process according to claim 17 , wherein the metal layer penetrates into the at least one through opening of the mask layer.

19. The process according to claim 17 , wherein selectively etching comprises plasma-etching.

20. The process according to claim 17 , wherein forming the metal layer is carried out in a vacuum to obtain an integrated microminiature vacuum-tube device.

Assignees

• St Microelectronics Srl

Inventors

• Fiumara Antonino

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H01J9/025 Primary

  of field emission cathodes · CPC title

• H01J21/105

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title