Display panel

Patent metadata

Field	Value
Publication number	US-9553203-B2
Application number	US-201414506061-A
Country	US
Kind code	B2
Filing date	Oct 3, 2014
Priority date	Jan 13, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A display panel includes a base substrate including a pixel area and a peripheral area, a semiconductor layer disposed on a portion of the base substrate, a display element disposed in the pixel area, and a thin film transistor which controls the display element and includes an input electrode, an output electrode and a control electrode, in which the semiconductor layer includes a first portion disposed on the input electrode of the first thin film transistor, a second portion disposed on the output electrode of the first thin film transistor, and a third portion which connects the first portion and the second portion, overlaps the control electrode of the first thin film transistor, and defines a channel of the first thin film transistor.

First claim

What is claimed is:

1. A display panel comprising:
a base substrate comprising a pixel area and a peripheral area;
a semiconductor layer disposed on a portion of the base substrate;
a display element disposed in the pixel area; and
a first thin film transistor which controls the display element and comprises an input electrode, an output electrode and a control electrode,
wherein the semiconductor layer comprises:
a first portion disposed on the input electrode of the first thin film transistor, and the first portion covering the input electrode;
a second portion disposed on the output electrode of the first thin film transistor, and the second portion covering the output electrode; and
a third portion overlapping the control electrode of the first thin film transistor and defining a channel of the first thin film transistor,
wherein the third portion is directly connected to the first portion and the second portion so as to form one body with the first portion and the second portion.

2. The display panel of claim 1 , wherein the semiconductor layer comprises a metal oxide semiconductor material.

3. The display panel of claim 2 , wherein the first thin film transistor further comprises:
an insulating pattern portion disposed on the semiconductor layer to overlap a portion of the third portion,
wherein the control electrode of the first thin film transistor is disposed on the insulating pattern portion.

4. The display panel of claim 3 , wherein the third portion comprises:
an input region connected to the first portion and comprising a reduced metal from the metal oxide semiconductor material;
an output region connected to the second portion and comprising the reduced metal from the metal oxide semiconductor material; and
a channel region disposed between the input region and the output region to connect the input region and the output region, wherein the channel region overlaps the insulating pattern portion.

5. The display panel of claim 2 , further comprising:
an insulating layer disposed between the control electrode of the first thin film transistor and the semiconductor layer,
wherein the control electrode is disposed to face the semiconductor layer and is disposed under the third portion.

6. The display panel of claim 5 , wherein the third portion comprises:
an input region connected to the first portion and comprising a reduced metal from the metal oxide semiconductor material;
an output region connected to the second portion and comprising the reduced metal from the metal oxide semiconductor material; and
a channel region disposed between the input region and the output region to connect the input region and the output region, wherein the channel region overlaps the control electrode.

7. The display panel of claim 6 , wherein the first thin film transistor further comprises:
a protection pattern portion disposed on the channel region of the third portion.

8. The display panel of claim 2 , further comprising:
a data line disposed in the peripheral area, connected to the input electrode of the first thin film transistor, and extending substantially in a first direction,
wherein the semiconductor layer further comprises a line portion connected to the first portion and which overlaps the data line.

9. The display panel of claim 8 , wherein the line portion has a width in a second direction, which is substantially perpendicular to the first direction, substantially the same as a width of the data line in the second direction.

10. The display panel of claim 9 , further comprising:
a gate line disposed in the peripheral area, connected to the control electrode, and extending substantially in the second direction.

11. The display panel of claim 9 , wherein the line portion comprises a reduced metal from the metal oxide semiconductor material.

12. The display panel of claim 1 , further comprising:
a second thin film transistor which controls a driving current flowing through the display element; and
a capacitor comprising:
a lower electrode connected to the output electrode; and
an upper electrode connected to the control electrode,
wherein the display element comprises an organic light emitting diode.

13. The display panel of claim 12 , wherein the organic light emitting diode comprises:
a first electrode connected to an output electrode of the second thin film transistor;
an organic light emitting layer disposed on the first electrode; and
a second electrode disposed on the organic light emitting layer.

14. The display panel of claim 12 , wherein the semiconductor layer further comprises:
a capacitance portion connected to the second portion and disposed on the lower electrode of the capacitor.

15. The display panel of claim 1 , further comprising:
an opposite substrate disposed opposite to the base substrate; and
a liquid crystal layer interposed between the base substrate and the opposite substrate,
wherein the display element comprises a liquid crystal capacitor.

16. A display panel comprising:
a base substrate comprising a pixel area and a peripheral area;
a conductive layer disposed on the base substrate;
a metal oxide semiconductor layer disposed on portions of the conductive layer;
a display element disposed in the pixel area; and
a thin film transistor which controls the display element,
wherein the thin film transistor comprises:
an input electrode comprising a first portion of the conductive layer, and a first portion of the metal oxide semiconductor layer disposed on the first portion of the conductive layer;
an output electrode comprising a second portion of the conductive layer, and a second portion of the metal oxide semiconductor layer disposed on the second portion of the conductive layer;
a channel defined by a third portion of the metal oxide semiconductor layer directly connected to the first portion of the metal oxide semiconductor layer and the second portion of the metal oxide semiconductor layer; and
a control electrode which is disposed on the third portion of the metal oxide semiconductor layer and insulated from the third portion of the metal oxide semiconductor layer, and
wherein the first portion of the metal oxide layer covers the first portion of the conductive layer and the second portion of the metal oxide layer covers the second portion of the conductive layer, and
wherein the first portion, the second portion, and the third portion of metal oxide semiconductor form one body.

17. The display panel of claim 16 , wherein the thin film transistor further comprises:
an insulating pattern portion disposed on the metal oxide semiconductor layer to overlap a portion of the third portion of the metal oxide semiconductor layer,
wherein the control electrode is disposed on the insulating pattern portion.

18. The display panel of claim 16 , wherein the third portion of the metal oxide semiconductor layer comprises:
an input region connected to the first portion of the metal oxide semiconductor layer and comprising a reduced metal from the metal oxide semiconductor layer;
an output region connected to the second portion of the metal oxide semiconductor layer and comprising the reduced metal from the metal oxide semiconductor layer; and
a channel region disposed between the input region and the output region to connect the input region and the output region.

19. The display panel of claim 16 , further comprising:
an insulating layer disposed between the control electrode and the semiconductor layer,
wherein the control elec

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Seung-Hwan
• Khang Yoonho
• Na Hyunjae
• Shin Youngki
• Shim Donghwan

Classifications

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title