Array substrate and method of manufacturing the same, display panel and method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-9553112-B2
Application number	US-201615082932-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Jun 19, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

The invention discloses an array substrate, a display panel and methods of manufacturing the same, and a display device. The array substrate comprises: a pixel region and a wiring region located outside the wiring region; a gate line and a data line each arranged within both the pixel and wiring regions; a passivation layer arranged to cover the gate and data lines and provided therein with trenches respectively exposing and being wider than the gate and data lines within the wiring region; first and second signal line partially arranged within the trenches respectively and contacting exposed portions of the gate and data lines to transmit signals to the gate and gate lines respectively, the first and second signal line each having widths equal to those of the trenches respectively. With the invention, good electrical connections between the signal line and the gate and data lines are enabled.

First claim

What is claimed is:

1. An array substrate, comprising:
a pixel region and a wiring region, the pixel region being arranged inside the wiring region;
a gate line arranged within the pixel region and the wiring region and comprising a first portion extending over a first length within the wiring region;
a data line arranged within the pixel region and the wiring region and comprising a second portion extending over a second length within the wiring region;
a passivation layer provided within the pixel region and the wiring region and covering the gate line and the data line, a portion of the passivation layer within the wiring region being provided therein with a first trench, from which at least the first portion of the gate line is exposed and which has a width larger than a width of the first portion of the gate line, and/or a portion of the passivation layer within the wiring region being provided therein with a second trench, from which at least the second portion of the data line is exposed and which has a width larger than a width of the second portion of the data line;
a first signal line partially arranged within the first trench and covering and contacting the portion of the gate line exposed from first trench so as to transmit a first signal to the gate line, a portion of the first signal line arranged within the first trench having a width equal to the width of the first trench; and
a second signal line, partially arranged within the second trench and covering and contacting the portion of the data line exposed from second trench so as to transmit a second signal to the data line, a portion of the second signal line arranged within the second trench having a width equal to the width of the second trench.

2. The array substrate according to claim 1 , wherein an end of the portion of the gate line extending into the wiring region and/or an end of the portion of the data line extending into the wiring region is located inside an outer edge of the wiring region.

3. The array substrate according to claim 2 , further comprising:
a base substrate, on which the gate line is arranged; and
a gate insulation layer arranged on the gate line, wherein the data line is arranged on the gate insulation layer.

4. The array substrate according to claim 3 , wherein
the sum of a thickness of the gate line and a thickness of the first signal line is equal to the sum of a thickness of the passivation layer and a thickness of the gate insulation layer, and/or
the sum of a thickness of the data line and a thickness of the second signal line is equal to the thickness of the passivation layer.

5. The array substrate according to claim 1 , wherein
the first signal line completely covers and directly contacts the first portion of a corresponding gate line within the wiring region, and is electrically insulated from adjacent gate lines; and/or
the second signal line completely covers and directly contacts the second portion of a corresponding data line within the wiring region, and is electrically insulated from adjacent data lines.

6. The array substrate according to claim 5 , further comprising:
a base substrate, on which the gate line is arranged; and
a gate insulation layer arranged on the gate line, wherein the data line is arranged on the gate insulation layer.

7. The array substrate according to claim 6 , wherein
the sum of a thickness of the gate line and a thickness of the first signal line is equal to the sum of a thickness of the passivation layer and a thickness of the gate insulation layer, and/or
the sum of a thickness of the data line and a thickness of the second signal line is equal to the thickness of the passivation layer.

8. The array substrate according to claim 1 , further comprising:
a base substrate, on which the gate line is arranged; and
a gate insulation layer arranged on the gate line, wherein the data line is arranged on the gate insulation layer.

9. The array substrate according to claim 8 , wherein
the sum of a thickness of the gate line and a thickness of the first signal line is equal to the sum of a thickness of the passivation layer and a thickness of the gate insulation layer, and/or
the sum of a thickness of the data line and a thickness of the second signal line is equal to the thickness of the passivation layer.

10. A display panel comprising the array substrate according to claim 1 , the display panel further comprising:
a color filter substrate assembled together with the array substrate,
wherein a region between a boundary of the color filter substrate and a boundary of the array substrate is the wiring region.

11. The display panel according to claim 10 , wherein the array substrate further comprises:
a reserved region arranged inside the wiring region and outside the pixel region,
wherein the reserved region is located between the boundary of the color filter substrate and a boundary of the pixel region.

12. The display panel according to claim 11 , wherein
a portion of the first trench extends into the reserved region and does not extend into the pixel region, and/or
a portion of the second trench extends into the reserved region and does not extend into the pixel region.

13. The display panel according to claim 10 , wherein an end of the portion of the gate line extending into the wiring region and/or an end of the portion of the data line extending into the wiring region is located inside an outer edge of the wiring region.

14. The display panel according to claim 10 , wherein
the sum of a thickness of the gate line and a thickness of the first signal line is equal to the sum of a thickness of the passivation layer and a thickness of the gate insulation layer, and/or
the sum of a thickness of the data line and a thickness of the second signal line is equal to the thickness of the passivation layer.

15. A display device, comprising the display panel according to claim 10 .

16. A method of manufacturing an array substrate, the array substrate comprising a pixel region and a wiring region located outside the pixel region, the method comprising:
forming a gate line and a data line within the pixel region and the wiring region, wherein the gate line comprises a first portion extending over a first length within the wiring region, and the data line comprises a second portion extending over a second length within the wiring region;
forming a passivation layer within the pixel region and the wiring region to cover the gate line and the data line;
etching the passivation layer to form a first trench in the passivation layer, at least the first portion of the gate line being exposed from the first trench and the first trench having a width larger than a width of the first portion of the gate line, and/or to form a second trench in the passivation layer, at least the second portion of the data line being exposed from the second trench and the second trench having a width larger than a width of the second portion of the data line;
forming a first signal line, such that the first signal line is partially located within the first trench and covers and contacts the first portion of the gate line to transmit a first signal to the gate line, a width of a portion of the first signal line located within the first trench being equal to the width of the first trench; and
forming a second signal line, such that the second signal line is partially located within the second trench and covers and contacts the second portion of the data line to transmit a second signal to the data line, a width of a portion of the second signal line located within th

Assignees

• Boe Tech Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Liping

Classifications

• H01L27/1259

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• G02B5/22

  Absorbing filters {(G02B5/201 - G02B5/208 take precedence)} · CPC title

• H01L29/42356

  Electricity · mapped topic

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title