Memory cell profiles

Patent metadata

Field	Value
Publication number	US-9553103-B2
Application number	US-201514593475-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Feb 9, 2012
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials.

First claim

What is claimed is:

1. A method of processing a memory cell, comprising:
removing a column from a material to define a profile for the memory cell, wherein the memory cell has a cross-sectional shape in a plane perpendicular to the column including a circular portion and at least one projecting rectangular portion;
partially filling an outer portion of the column including the circular portion and the at least one projecting rectangular portion with a first number of materials, wherein one of the first number of materials comprises a charge storage material; and
filling a remaining portion of the column with a second number of materials.

2. The method of claim 1 , wherein removing the column comprises:
removing the circular portion in a first stage; and
removing the at least one projecting rectangular portion in a second stage.

3. The method of claim 1 , wherein filling the outer portion of the column with the first number of materials comprises:
partially filling the column from the outer portion of the column towards an inner portion of the column.

4. The method of claim 3 , wherein filling the remaining portion of the column with the second number of materials comprises:
filling the inner portion of the column including the circular portion and the at least one projecting rectangular portion from the outer portion towards the inner portion.

5. The method of claim 1 , wherein removing the column comprises removing the column through a reactive ion etching process.

6. The method of claim 1 , further comprising removing the column in a single stage.

7. The method of claim 1 , wherein removing the at least one projecting rectangular portion comprises removing a first projecting rectangular portion and a second projecting rectangular portion at opposite ends of the circular portion.

8. The method of claim 1 , wherein the first number of materials further include a first dielectric material and a second dielectric material and the second number of materials include a third dielectric material and a conductor material.

9. The method of claim 8 , wherein the conductor material comprises a polysilicon, the first and the third dielectric materials comprise an oxide, and the second dielectric material comprises one of an oxide and a nitride.

10. A three-dimensional memory device comprising:
a plurality of memory cells in a column formed in a first material, wherein the plurality of memory cells have a cross-sectional shape in a plane perpendicular to the column including a circular portion and at least one projecting rectangular portion, wherein:
an outer portion of the column including the circular portion and the at least one projecting rectangular portion includes a first number of materials formed therein, wherein one of the first number of materials comprises a charge storage material; and

an inner portion of the column includes a second number of materials formed therein.

11. The device of claim 10 , wherein the inner portion of the column includes the circular portion and the outer portion of the column includes the circular portion and the projecting rectangular portion.

12. The device of claim 10 , wherein at least one of the second number of materials is formed only in the circular portion of the column.

13. The device of claim 10 , wherein the plurality of memory cells have a plurality of projecting rectangular portions are spaced apart around the circular portion.

14. The device of claim 10 , wherein the charge storage material comprises polysilicon.

15. A three-dimensional memory device comprising:
a plurality of memory cells in a plurality of columns formed in a material, wherein the plurality of memory cells each have a cross-sectional shape in a plane perpendicular to the plurality of columns including a circular portion and a projecting rectangular portion, wherein:
a first column and a second column of the plurality columns are aligned in a first line;
a third column and a fourth column of the plurality columns are aligned in a second line; and
wherein the first line is parallel to the second line;
wherein the projecting rectangular portions of the memory cells in the first column and second column are oriented in a first direction; and
wherein the projecting rectangular portions of the memory cells in the third column and fourth column are oriented in a second direction different than the first direction.

16. The device of claim 15 , wherein the material comprises a first conductor material and wherein the plurality of columns include:
an outer portion that comprises a first dielectric material, a second dielectric material, and a second conductor material; and
an inner portion that comprises a third dielectric material and a third conductor material.

17. The device of claim 16 , wherein the first dielectric material is conformal to the first conductor material, the second dielectric material is conformal to the first dielectric material, the second conductor material is conformal to the second dielectric material, the third dielectric material is conformal to the second conductor material, and the third conductor material is conformal to the third dielectric material.

18. The device of claim 16 , wherein the second conductor material is a charge storage material.

19. The device of claim 15 , wherein the third column is positioned at an equal distance from the first and the second columns.

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic