Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9553094-B2
Application number	US-201615069920-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Mar 19, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate on which a first region and a second region are defined;
first and second gate structures arranged on the first and second regions, respectively; and
a capping layer covering the first and second gate structures,
wherein the first gate structure includes a first interface layer arranged on the substrate, a first high-k dielectric layer arranged on the first interface layer, a first diffusion layer arranged on the first high-k dielectric layer, a first barrier layer arranged on the first diffusion layer, a first work function adjustment layer arranged on the first barrier layer, a third barrier layer arranged on the first work function adjustment layer, and a gate metal arranged on the first work function adjustment layer, and
wherein the second gate structure includes a second interface layer arranged on the substrate, a second high-k dielectric layer arranged on the second interface layer, a second diffusion layer arranged on the second high-k dielectric layer, a second barrier layer arranged on the second diffusion layer, a second work function adjustment layer arranged on the second barrier layer, a third work function adjustment layer arranged on the second work function adjustment layer, and a fourth barrier layer arranged on the third work function adjustment layer.

2. The semiconductor device of claim 1 , further comprising:
a first fin projecting from the first region and extending in a first direction; and
a second fin projecting from the second region and extending in the first direction,
wherein the first gate structure is arranged on the first fin to cross the first fin, and the second gate structure is arranged on the second fin to cross the second fin.

3. The semiconductor device of claim 1 , wherein the first work function adjustment layer and the third work function adjustment layer include the same material.

4. The semiconductor device of claim 1 , wherein the number of layers included in the first gate structure is different from the number of layers included in the second gate structure.

5. The semiconductor device of claim 1 , wherein the capping layer includes at least one of SiN, SiON, and SiCON.

6. The semiconductor device of claim 1 , wherein the first region includes an NFET region, and the second region includes a PFET region.

7. The semiconductor device of claim 1 , wherein a thickness of the first barrier layer is 3 to 30 Å.

8. The semiconductor device of claim 1 , wherein the diffusion layer and the first barrier layer comprise different materials.

9. The semiconductor device of claim 8 , wherein the diffusion layer comprises Ti, and the first barrier layer comprises Ta.

10. The semiconductor device of claim 1 , wherein a thickness of the capping layer is 5 to 500 Å.

11. The semiconductor device of claim 10 , wherein the capping layer comprises an oxide layer.

12. The semiconductor device of claim 10 , wherein the capping layer comprises a nitride layer.

Assignees

• Tseng Wei-Hsiung
• Kim Ju-Youn
• Won Seok-Jun
• Lee Jong-Ho
• Lee Hye-Lan
• Ha Yong-Ho
• Samsung Electronics Co Ltd

Inventors

• Tseng Wei-Hsiung
• Kim Ju-Youn
• Won Seok-Jun
• Lee Jong-Ho
• Lee Hye-Lan
• Ha Yong-Ho

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title